Semiconductor and method for producing same

Abstract

The invention discloses a method for producing a semiconductor, which comprises the following steps: providing a substrate; forming a grid oxide layer and a grid electrode on the substrate; forming a clearance wall insulating layer on the grid oxide layer and the side wall of the grid electrode, and meanwhile, forming a first insulating layer on the back of the substrate; forming a clearance wallon the side wall of the clearance wall insulating layer, and meanwhile, forming a second insulating wall on the side wall of the first insulating layer; forming a source electrode and a drain electrode on the substrate; forming an etching stop layer on the clearance wall; forming a high-stress inductive layer on the etching stop layer; etching the high-stress inductive layer to thin the high-stress inductive layer; forming a first oxide layer on the thinned high-stress inductive layer, and meanwhile, forming a second oxide layer on the back of the second insulating layer; etching the first oxide layer to remove the first oxide layer; etching the thinned high-stress inductive layer and the etching stop layer to remove the thinned high-stress inductive layer and the etching stop layer.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a manufacturing process for preventing semiconductor devices from being damaged by plasma. Background technique [0002] The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Considering the excellent characteristics of operation speed, power consumption and cost efficiency, CMOS technology is currently one of the most promising methods for manufacturing complex circuits. In the fabrication of complex integrated circuits using CMOS technology, millions of transistors (eg, N-channel transistors and P-channel transistors) are formed on a substrate comprising crystalline semiconductor layers. Regardless of whether N-channel or P-channel transistors are being studied, MOS transistors contain a so-called PN junction formed by the interface of a highly doped drain / source ...

AI Technical Summary

Problems solved by technology

This movement of charges in the semiconductor device 100 causes a discharge current (as indicated by an arrow in the figure) to be generated from the gate electrode 103 to the substrate 101, and this discharge current will destroy the gate electrode 103, thereby deteriorating the characteristics of the semiconductor device. Poor, which produces so-called plasma damage (PID), which destroys the performance of the device

[0014] Therefore, there is a need for a method that can effectively overcome the problem of plasma damage to semiconductor devices after SMT processing, so as to reduce the cost of semiconductor device production and improve yield

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