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Double-flat integrated circuit (IC) chip packaging part with short pins and manufacturing method thereof

A chip package, double-flat technology, applied in the field of electronic information automation components manufacturing, can solve the problems of difficult process control, large warpage, low lead frame production efficiency, etc., achieve good economic and social benefits, manufacturing The effect of low cost, convenient maintenance and inspection

Active Publication Date: 2013-04-17
TIANSHUI HUATIAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide an IC with double flat short pins for the problems of low production efficiency, single-sided packaging, large warpage, and difficult process control of the lead frame produced by etching for the existing DFN and QFN. Chip package, the invention also provides the production method of the package

Method used

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  • Double-flat integrated circuit (IC) chip packaging part with short pins and manufacturing method thereof
  • Double-flat integrated circuit (IC) chip packaging part with short pins and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Wafer thinning→scribing→chip-on→pressure welding→plastic sealing→post-curing→electroplating→printing→punching and separation→inspection→packaging→warehousing.

[0054] 1. Wafer thinning and dicing

[0055] The thickness of this package product is 0.75mm, and the final thinning thickness of the wafer is 220μm. The VG502mkⅡ8B automatic thinning machine is used, and the conventional coarse grinding and fine grinding processes are used.

[0056] Scribing uses DAD321 dicing machine, normal scribing process.

[0057] 2. Core loading

[0058] The DFL special lead frame made by stamping is used, the chip thickness is 220μm, the chip loading equipment is AD828 or AD829 chip bonder, and the environmentally friendly conductive adhesive 8352L is used. In the center of the chip machine, first put 8352L conductive adhesive on the frame carrier, then automatically absorb the chip and place it on the already-pointed conductive adhesive, stick all the chips in the same way, automatica...

Embodiment 2

[0080] 1. Wafer thinning and dicing

[0081] The thickness of this packaging product is 0.75mm, and the final thinning thickness of the wafer is the chip thickness of 180μm. The VG502mkⅡ8B automatic thinning machine is used, and the conventional coarse grinding and fine grinding processes are used.

[0082] Scribing uses DAD321 dicing machine, normal scribing process.

[0083] 2. Core loading

[0084] The DFL special lead frame made by stamping is used, the chip thickness is 180μm, the chip loading equipment is AD828 or AD829 chip bonder, the environment-friendly conductive adhesive 8352L is used, and the dispensing head and suction nozzle matching the chip size are selected. In the center of the chip machine, first put 8352L conductive adhesive on the frame carrier, then automatically absorb the chip and place it on the already-pointed conductive adhesive, stick all the chips in the same way, automatically receive the material to the delivery clip and send it to cure, using ...

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Abstract

The invention provides a double-flat integrated circuit (IC) chip packaging part with short pins, comprising a lead frame carrier, a sticky film adhesive, an IC chip, inner pins, bonding wires, outer pins and a plastic-packaged body, wherein the inner pins are on a same plane with the carrier upwards; the outer pins are exposed out of the plastic-packaged body; the sizes that the outer pins are exposed out of the plastic-packaged body are 0.15-0.35mm, and the exposed part and the plastic-packaged body are on the same plane; and the pin pitch is 0.4mm / 0.5mm / 0.65mm. The packaging part is of a double-surface package structure, and the carrier is not exposed. The technological process of the packaging part comprises the following steps: thinning a wafer; carrying out scribing; assembling a core; carrying out pressure welding; carrying out plastic packaging; carrying out post curing; electroplating; stamping; performing punching separation; inspecting; packaging; and warehousing. In the invention, the price of a lead frame is low, and the investment cost is less. A punching separation method has the advantages of high efficiency and low manufacturing cost compared with a cutting separation method. The product produced by the production method can be assembled by using reflow soldering and manual welding. The input cost of complete machine production equipment is less, and maintenance and inspection are convenient; and the method is more suitable for small-scale assembly production of various types of chips, and the use is flexible.

Description

technical field [0001] The invention relates to the technical field of electronic information automation component manufacturing, in particular to an IC chip integrated circuit package, specifically a double flat short lead IC chip package, and the invention also includes a production method of the package. Background technique [0002] With the rapid development of the electronic information industry, the chip manufacturing industry of electronic technology has entered the nanometer era. Electronic consumer products are becoming thinner and smaller to meet the needs of ultra-thin mobile phones, cameras and other portable electronic products. DFN and QFN packages are the preferred packaging forms. However, the production efficiency of the lead frame produced by etching in the existing conventional DFN and QFN production is low and cannot fully meet the production needs; there is an adhesive film (or UV adhesive film) on the back of the lead frame (L / F), and the cost of a sin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/31H01L21/50
CPCH01L2224/48091H01L2224/73265H01L2224/32245H01L2224/48247H01L2924/181
Inventor 郭小伟何文海慕蔚
Owner TIANSHUI HUATIAN TECH