Edge rate suppression for open drain buses

Abstract

An edge rate suppression circuit arrangement is provided for operation with an open drain bus. The circuit arrangement includes a variable resistive circuit having an input for receiving a variable voltage signal and an output coupled to the open drain bus, and a control circuit configured to operate the variable resistive circuit. The control circuit operates the variable resistive circuit in respective high and low resistance states in response to the variable voltage signal.

Description

Technical field [0001] The present invention generally relates to edge rate suppression of communication buses, and more specifically, to edge rate suppression in open drain buses. Background technique [0002] Such as the built-in integrated circuit bus, system management bus (SMBus) and other open-drain buses include data lines and clock lines. Inter-integrated circuit bus is usually called IIC, I2C or I 2 C bus, and will be referred to as I2C bus below. Each of the data line and the clock line may be referred to as a bus line, or simply a line, respectively. Each bus line is connected to a pull-up resistor, an interface device, and a capacitor, which represents the distributed capacitance of the bus line and the total input capacitance of the connected interface device. The data transfer rate depends on the speed at which the resistor can charge the capacitor. [0003] The I2C bus is used in a variety of implementations, including implementations involving servers and compute...

AI Technical Summary

Problems solved by technology

However, I2C pins on some devices (such as processors and ASICs) often use GPIO pins with high drive strength and no edge rate control

These approaches can lead to problems with overshoot and noise, which can involve, for example, droop rates at transitions that are shorter than the round-trip time of the I2C bus

A related problem arises due to the wave off of reflections at the end of the bus, which can lead to clamping and / or body diode conduction on components distributed along the bus

Other issues arise in compensating for fast transitions, as other characteristics of the I2C bus communication are affected, such as limitations on the voltage levels that can be used to drive the bus to logic low

[0004] Due to the above and other issues, the implementation of various devices with an I2C bus and the implementation of edge rate suppression for such devices remains a challenge

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