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Grid driving circuit

A gate drive circuit and circuit technology, applied in the direction of instruments, static indicators, etc., can solve problems such as large dynamic power consumption, and achieve the effect of reducing dynamic power consumption and reducing size

Active Publication Date: 2012-08-29
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, in order to ensure that the transistor switches coupled to the pixels are fully turned on, the high-level potential of the high-frequency clock pulse signal is usually higher than 25 volts, which causes greater dynamic power consumption.

Method used

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Embodiment Construction

[0021] Please refer to figure 1 , figure 1 A schematic diagram of the gate driving circuit 100 is illustrated for an embodiment of the present invention. The gate driving circuit 100 includes a multi-stage shift register 102 and a multi-stage buffer output circuit 104 , and only the nth-stage shift register 102 and the n-th stage buffer output circuit 104 are shown in the figure. Such as figure 1 As shown, the shift register 102 of the nth stage utilizes the low-frequency clock pulse signal LC, the first high-frequency clock pulse signal HC1, the third high-frequency clock pulse signal HC3, the reference low potential VSS, and the continuation of the n+2-th stage shift register The potential of the transmission node STN(n+2) and the potential of the output node G(n-2) of the n-2th stage buffer output circuit generate the potential of the continuous transmission node STN(n) of the nth stage shift register, the The potential of the first node Q(n) of the n-stage shift registe...

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PUM

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Abstract

The invention discloses a grid driving circuit, which comprises an nth-level shift register and an nth-level buffer output circuit. The potential of the continuous transmission node of the nth-level shift register is used as the input signal of an input transistor of an (n+2) -level shift register. The potential of the output node of the nth-level buffer output circuit is changed by using a high reference potential, a pull-down control signal, the potential of the first node of the nth-level shift register and the potential of the continuous transmission node of the (n+2) -level shift register or a first high-frequency clock pulse signal, wherein the potential of the output node of the nth-level buffer output circuit is used for controlling switch-on and switch-off of a switch coupled with a pixel, and the high reference potential is a direct-current voltage and higher than the high-level potential of a third high-frequency clock pulse signal.

Description

technical field [0001] The invention relates to a grid driving circuit, especially a low dynamic power grid driving circuit. Background technique [0002] In the prior art, since the pull-up transistor of the shift register is not only responsible for charging and discharging the scan lines on the liquid crystal display panel, it must also drive the pull-down transistor of the previous shift register and the input transistor of the next shift register. Therefore, the size of the pull-up transistor must be large, resulting in a larger parasitic capacitance of the pull-up transistor. Because the drain terminal of the pull-up transistor is used to receive the high-frequency clock signal, the large parasitic capacitance of the pull-up transistor will generate additional dynamic power consumption f*Cgd*V^2, where f is the frequency of the high-frequency clock signal , V is the voltage level difference of the high-frequency clock pulse signal and Cgd is the capacitance value of t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/36
Inventor 刘晋炜陈文彬
Owner AU OPTRONICS CORP