Touch panel

[0057] Reference will now be made in detail to several exemplary embodiments, and examples of the several exemplary embodiments are illustrated in the accompanying drawings. In addition, wherever possible, components with the same number are used in the drawings and embodiments to represent the same or similar parts.

[0058] figure 2 It is a functional block diagram of a touch panel 100 according to an embodiment of the present invention. Please refer to figure 2 In this embodiment, the touch panel 100 is assembled to become a liquid crystal display (LCD). However, the present invention should not be limited to this. For example, the touch panel 100 can also be assembled into a plasma display, a cathode ray tube (CRT) display, or a light-emitting diode (LED) display. The touch panel 100 is used to provide information to identify a portion of the touch panel 100 that has been touched, so that it generates navigation signals for operating electronic devices (such as personal computers, PDAs, mobile phones, etc.). The touch panel 100 has a panel capacitance Cp, a first capacitance Ca, and a second capacitance Cb. The panel capacitance Cp represents one of many capacitances in a liquid crystal display. In other words, the liquid crystal display may include a plurality of panel capacitors Cp, and these panel capacitors Cp are arranged in an array. When the user touches the touch panel 100, the capacitance value of the panel capacitor Cp will change according to the degree of contact force, so that the navigation signal can be generated according to the change of the capacitance value of the panel capacitor Cp.

[0059] The touch panel 100 further includes a first clock phase generator 22 and six switches SW1 to SW6. The six switches SW1 to SW6 are a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, and a sixth switch SW6, respectively. The first clock phase generator 22 generates a first phase signal according to the first clock signal CLK1 And the second phase signal image 3 It is a signal timing diagram of the touch panel 100. Please refer to image 3 , The first clock signal CLK1 is a periodic signal. In this embodiment, only when the first clock signal CLK1 is at a high level, the first phase signal It is at high level. Each in the first phase signal The duration at the high level is less than the duration of the first clock signal CLK1 at the high level. In addition, the second phase signal The high level is only when the first clock signal CLK1 is low. Each in the second phase signal The duration of the high level is less than the duration of the first clock signal CLK1 at the low level. Such as image 3 As shown, the first phase signal The duration at the high level does not differ from the second phase signal The durations at the high level overlap each other. In other words, the first phase signal And the second phase signal Will not be at high level at the same time.

[0060] Both the first switch SW1 and the third switch SW3 are based on the first phase signal The voltage level is turned on/off. In this embodiment, when the first phase signal When at a high level, the first switch SW1 and the third switch SW3 will be turned on. And the first switch SW1 and the third switch SW3 will be in the first phase signal It is cut off at low level. However, the present invention should not be limited to this. For example, in other embodiments of the present invention, when the first phase signal At low level, the first switch SW1 and the third switch SW3 will be turned on, and when the first phase signal When at a high level, the first switch SW1 and the third switch SW3 will be turned off.

[0061] Furthermore, the second switch SW2 and the fourth switch SW4 are based on the second phase signal The voltage level is turned on/off. In this embodiment, in the second phase signal When it is high, the second switch SW2 and the fourth switch SW4 will be turned on, and the second switch SW2 and the fourth switch SW4 will be in the second phase signal It is cut off at low level. However, the present invention should not be limited to this. For example, according to other embodiments of the present invention, when the second phase signal At low level, the second switch SW2 and the fourth switch SW4 will be turned on, and the second switch SW2 and the fourth switch SW4 will be in the second phase signal It ends when the bit is high.

[0062] The first terminal 32 of the first switch SW1 is coupled to the first reference voltage VR1, and the second terminal 34 of the first switch SW1 is coupled to the panel capacitor Cp. In addition, the first terminal 36 of the second switch SW2 is coupled to the panel capacitor Cp and the second terminal 34 of the first switch SW1. The second terminal 38 of the second switch SW2 is coupled to the fourth switch SW4. The first switch SW1 and the second switch SW2 will not be turned on at the same time. In this detailed description, on the one hand, when the first switch SW1 is turned on, the second switch SW2 will be turned off, so that the panel capacitor Cp is charged via the first reference voltage VR1. On the other hand, when the second switch SW2 is turned on, the first switch SW1 will be turned off, causing the panel capacitor Cp to release charges. Thereby, the panel capacitance Cp depends on the first phase signal And the second phase signal And periodically charge and discharge.

[0063] Similarly, the first terminal 42 of the third switch SW3 is coupled to the second reference voltage VR2, and the second terminal 44 of the third switch SW3 is coupled to the first capacitor Ca. In addition, the first end 46 of the fourth switch SW4 is coupled to the first capacitor Ca and the second end 44 of the third switch SW3, and the second end 48 of the fourth switch SW4 is coupled to the second end of the second switch SW2 38. The third switch SW3 and the fourth switch SW4 will not be turned on at the same time. In detail, on the one hand, when the third switch SW3 is turned on, the fourth switch SW4 will be turned off, so that the first capacitor Ca is charged via the second reference voltage VR2. On the other hand, when the fourth switch SW4 is turned on, the third switch SW3 will be turned off, so that the first capacitor Ca discharges charges. Thus, the first capacitor Ca is based on the first phase signal And the second phase signal And periodically charge and discharge.

[0064] Also because the first switch SW1 and the third switch SW3 are based on the first phase signal The panel capacitor Cp and the first capacitor Ca are charged simultaneously by the first reference voltage VR1 and the second reference voltage VR2, respectively. Furthermore, because the second switch SW2 and the fourth switch SW4 are based on the second phase signal The panel capacitor Cp and the first capacitor Ca will simultaneously discharge charges.

[0065] The touch panel 100 further includes a control circuit 60. One input terminal of the control circuit 60 is coupled to the second terminal 38 of the second switch SW2 and the second terminal 48 of the fourth switch SW4. The control circuit 60 is based on the third reference voltage VR3 and the voltage level V of the second terminal 38 of the second switch SW2 O To generate the third phase signal And the fourth phase signal Third phase signal And the fourth phase signal Are provided to the fifth switch SW5 and the sixth switch SW6, respectively, so that the fifth switch SW5 and the sixth switch SW6 are based on the third phase signal And the fourth phase signal To turn on/off. The fifth switch SW5 and the sixth switch SW6 will not be turned on at the same time. In detail, in one aspect of this embodiment, when the fifth switch SW5 is turned on, the sixth switch SW6 will be turned off, so that the second capacitor Cb is charged via the second reference voltage VR2. On the other hand, when the sixth switch SW6 is turned on, the fifth switch SW5 will be turned off, so that the second capacitor Cb discharges charges. Thus, the second capacitor Cb is based on the third phase signal And the fourth phase signal And periodically charge and discharge.

[0066] The first reference voltage VR1, the second reference voltage VR2 and the third reference voltage VR3 are adjustable. In the embodiment of the present invention, the relationship between the three reference voltages VR1, VR2, and VR3 is as follows:

[0067] K×(VR1-VR3)=N×(VR3-VR2)..........................(1)

[0068] Each parameter K and N can be any real number.

[0069] In the embodiment of the present invention, the parameters K and N are 1. The first reference voltage VR1 is 1 Volt (Volt, V for short), the second reference voltage VR2 is 3V, and the third reference voltage VR3 is 2V. However, the present invention should not be limited to this. When the fifth switch SW5 and the sixth switch SW6 are both turned off and stop operating, the voltage level of the second terminal 38 of the second switch SW2 is V O It will be determined according to the capacitance values ​​of the panel capacitance Cp and the first capacitance Ca. That is:

[0070] V O = VR 1 X Cp + VR 2 X Ca Cp + Ca = Cp + 3 X Ca Cp + Ca ( volts ) . . . . . . ( 2 )

[0071] According to equation (2), when the capacitance value of the panel capacitor Cp is equal to the capacitance value of the first capacitor Ca, the voltage level V O Will be equal to 2V (that is, the third reference voltage VR3). Furthermore, when the capacitance value of the panel capacitor Cp is smaller than the capacitance value of the first capacitor Ca, the voltage level V O Will be greater than 2V, and when the capacitance value of the panel capacitor Cp is greater than the first capacitor Ca, the voltage level V O Will be less than 2V.

[0072] The control circuit 60 according to the voltage level V O And the third reference voltage VR3 to generate the third phase signal And the fourth phase signal In this way, the actions of the fifth switch SW5 and the sixth switch SW6 are controlled. In detail, when the voltage level V O Less than the third reference voltage VR3, and the control circuit 60 has detected the first phase signal At one of the rising edges, the control circuit 60 is in the third phase signal A corresponding pulse is generated in it. Since the third phase signal Each pulse generated in the control circuit 60 facilitates the detection of the next second phase signal When the rising edge of, correspondingly generates a fourth phase signal In the pulse.

[0073] Similarly, when the voltage level V O Greater than the third reference voltage VR3, and when the control circuit 60 detects the first phase signal When the rising edge of the control circuit 60 makes the third phase signal The voltage level is at low level. And because the third phase signal Low level, when the control circuit 60 detects the second phase signal When the next rising edge of, the fourth phase signal The voltage level becomes low.

[0074] In the embodiment of the present invention, the control circuit 60 calculates the third phase signal within a predetermined period (for example, 1 microsecond (ms)) Number of pulses N C. The control circuit 60 depends on the number of pulses N C From capacitance C 1 To C N The first capacitor Ca is selected in, and the capacitance value of the selected first capacitor Ca is smaller than the capacitance value of the panel capacitor Cp. Since the capacitance value of the selected first capacitor Ca is smaller than the capacitance value of the panel capacitor Cp, the voltage level V O Often smaller than the third reference voltage VR3. In order to make the voltage level V O Can be close to the third reference voltage VR3, the second capacitor Cb, the fifth switch SW5 and the sixth switch SW6 are used to compensate the voltage level V O The voltage difference with the third reference voltage VR3. For example, in the embodiment of the present invention, the capacitance value of the panel capacitor Cp is 20.5 pF, the capacitance value of the first capacitor Ca is 20 pF, and the capacitance value of the second capacitor is 1 pF. When the touch panel 100 is operating, the control circuit 60 turns on/off the fifth switch SW5 and the sixth switch SW6 at an appropriate time, so that the voltage level V O Swing near the third reference voltage VR3, such as image 3 As shown, in detail, when the control circuit 60 detects the voltage level V O When it is less than the third reference voltage VR3, the control circuit 60 will successively turn on the fifth switch SW5 and the sixth switch SW6 to increase the voltage level V O. When the control circuit 60 detects the voltage level V O When it is greater than the third reference voltage VR3, the control circuit 60 will successively turn off the fifth switch SW5 and the sixth switch SW6 to pull down the voltage level V O.

[0075] The frequency of turning on the fifth switch SW5 and the sixth switch SW6 is related to the capacitance difference between the panel capacitance Cp and the first capacitance Ca. For example, in this embodiment, the capacitance difference between the panel capacitor Cp and the first capacitor Ca is equal to 0.5 (ie 20.5-20) pF, and the capacitance value of the second capacitor Cb is equal to 1 pF, so that the capacitance difference between Cp and Ca The ratio of the value to the capacitance value of the second capacitor is equal to 0.5 (ie 0.5/1). The control circuit 60 is configured to control the third phase signal within a predetermined period (Or the fourth phase signal ) The number of pulses and the first phase signal (Or the second phase signal The ratio of the number of pulses in) is equal to 0.5 (that is, the ratio of the capacitance difference between Cp and Ca to the capacitance of the second capacitor Cb). For example, such as image 3 As shown, when the first phase signal is generated Ten pulses and the second phase signal Of ten pulses, the third phase signal will be generated at the same time Five pulses and the fourth phase signal Of five pulses. Thus, the pulse ratio is 0.5 (ie, 5/10), and the pulse ratio is equal to the ratio of the capacitance difference between Cp and Ca and the capacitance of the second capacitor Cb.

[0076] Please refer to Figure 4 , Figure 4 It is a signal timing diagram of the touch panel 100, in which the capacitance value of the panel capacitor Cp is changed to 20.75 pF. The capacitance value of the first capacitor Ca is still 20 pF, and the capacitance value of the second capacitor Cb is still 1 pF. Therefore, in this embodiment, the ratio of the capacitance difference between Cp and Ca to the capacitance of the second capacitor Cb is 0.75 (ie, 0.75/1). Furthermore, as Figure 4 As shown, when the first phase signal is generated Eight pulses and the second phase signal Of eight pulses, the third phase signal will be generated at the same time Six pulses and the fourth phase signal Of six pulses. The ratio of six to eight is 0.75, which is equivalent to the ratio of the capacitance difference between Cp and Ca and the capacitance of the second capacitor Cb.

[0077] Please refer to Figure 5 , Figure 5 It is a signal timing diagram of the touch panel 100, in which the capacitance value of the panel capacitance Cp is changed to 20.25 pF. The capacitance value of the first capacitor Ca is still 20 pF, and the capacitance value of the second capacitor Cb is still 1 pF. Therefore, in this embodiment, the ratio of the capacitance difference between Cp and Ca and the capacitance of the second capacitor Cb is 0.25 (ie 0.25/1). Furthermore, as Figure 5 As shown, when the first phase signal is generated Eight pulses and the second phase signal When eight pulses of, the third phase signal will be generated at the same time Two pulses and the fourth phase signal Of two pulses. The ratio of two to eight is 0.25, which is equivalent to the ratio of the capacitance difference between Cp and Ca and the capacitance of the second capacitor Cb.

[0078] In short, when the voltage level V O When it is less than the third reference voltage VR3, the fifth switch SW5 and the sixth switch SW6 will be turned on successively to increase the voltage level V O. When the voltage level V O When the voltage is greater than the third reference voltage VR3, the control circuit 60 stops turning on the fifth switch SW5 and the sixth switch SW6 until the voltage level V O Less than the third reference voltage VR3. Therefore, the control circuit 60 uses the fifth switch SW5 and the sixth switch SW6 to compensate the voltage level V O The voltage difference with the third reference voltage VR3.

[0079] Since the third phase signal within the predetermined period (Or the fourth phase signal ) Number of pulses and the first phase signal within a predetermined period (Or the second phase signal Since the ratio of the number of pulses is equal to the ratio of the capacitance difference between Cp and Ca and the capacitance of the second capacitor Cb, the capacitance value of the panel capacitor Cp can be determined according to the following:

[0080] Cp=C1+C2×R.........................................(3 )

[0081] Among them, R is the third phase signal within a predetermined period (Or the fourth phase signal ) Number of pulses and the first phase signal within a predetermined period (Or the second phase signal ) Ratio of the number of pulses.

[0082] For example, when the ratio R is equal to 0.5, such as image 3 As shown, the capacitance value of the panel capacitance Cp is equal to (Ca+Cb×0.5). Such as Figure 4 As shown, when the ratio R is equal to 0.75, the capacitance value of the panel capacitance Cp is equal to (Ca+Cb×0.75). Such as Figure 5 As shown, when the ratio R is equal to 0.25, the capacitance value of the panel capacitance Cp is equal to (Ca+Cb×0.25). If the ratio is equal to 1, it means that the capacitance value of the panel capacitance Cp may be greater than or equal to (Ca+Cb), so that the control circuit 60 needs to be from the capacitance C 1 To C N Choose another capacitor with a higher capacitance value to replace the original first capacitor Ca. For example, when the capacitance value of the panel capacitor Cp is 21.25 pF, it is already greater than the sum of the capacitance values ​​of the first capacitor Ca (20 pF) and the second capacitor Cb (1 pF), N C Will be equal to a predetermined value, and the signal processor 96 of the control circuit 60 is 1 To C N Choose another capacitor with a capacitance value of 21pF to replace the original capacitor Ca. Therefore, the panel capacitance Cp will be less than (Ca+Cb) but greater than Ca, that is, Ca

[0083] Image 6 It is a functional block diagram of the touch panel 100a according to an embodiment of the invention. The touch panel 100a is similar to figure 2 的touch panel 100. The touch panel 100a also includes a panel capacitor Cp, a first capacitor Ca, a second capacitor Cb, a first clock phase generator 22, six switches SW1-SW6, and a control circuit 60a. The connection relationship between the panel capacitance Cp, the first capacitance Ca, the second capacitance Cb, the first clock phase generator 22 and the six switches SW1-SW6 in the touch panel 100a and their functions are related to the panel capacitance Cp and the first A capacitor Ca, a second capacitor Cb, and the first clock phase generator 22 are the same as the six switches SW1-SW6. The control circuit 60a is used for according to the third reference voltage VR3, the voltage level V O , The first phase signal And the second phase signal And generate the third phase signal And the fourth phase signal The control circuit 60a has an integrator 70, an operational amplifier 80 and a latch circuit 90. The integrator 70 is based on the third reference voltage VR3 and the voltage level V of the second terminal 38 of the second switch SW2 O To output the integral signal S i. The first input terminal 72 of the integrator 70 is coupled to the third reference voltage VR3. The second input terminal 74 of the integrator 70 is coupled to the second terminal 38 of the second switch SW2, the second terminal 48 of the fourth switch SW4, and the second terminal 58 of the sixth switch SW6. The integrator 70 has an operational amplifier 76 and an integrating capacitor Ci. The two input terminals of the operational amplifier 76 are respectively coupled to the first input terminal 72 and the second input terminal 74 of the integrator 70. The integrating capacitor Ci is coupled between one of the input terminals and the output terminal of the operational amplifier 76.

[0084] Figure 7 It is a signal timing diagram of the touch panel 100a. Please refer to Image 6 versus Figure 7 , When the voltage level V O When less than the third reference voltage VR3, the integral signal S i The voltage level of is greater than the third reference voltage VR3. When the voltage level V O When greater than the third reference voltage VR3, the integral signal S i The voltage level of is less than the third reference voltage VR3.

[0085] The operational amplifier 80 compares the third reference voltage VR3 with the integral signal S i Amplify the signal S with output OP. The first input terminal 82 of the operational amplifier 80 is coupled to the third reference voltage VR3, and the second input terminal 84 of the operational amplifier 80 is coupled to the output terminal of the integrator 70. When the integral signal S i When greater than the third reference voltage VR3, the signal S is amplified OP At high level. When the signal S is amplified i When less than the third reference voltage VR3, amplify the signal S OP At low level.

[0086] The latch circuit 90 is coupled to the output terminal of the operational amplifier 80. The latch circuit 90 temporarily stores the large signal S according to the first clock signal CLK1 OP To output the latch signal S L To the logical operator 94. In detail, when the signal S is amplified OP When the signal is at high level and the rising edge of the first clock signal CLK1 is detected, the signal S is latched L Will be pulled to high level. And, when the signal S is amplified OP When it is at a low level and the rising edge of the first clock signal CLK1 is detected, the signal S will be latched L Pull down to low level.

[0087] The control circuit 60a also includes a counter 92. The counter 92 calculates the latch signal S within a predetermined period L Number of pulses N C , And the touch panel 110a depends on the number of pulses N C To calculate the capacitance value of the panel capacitance Cp. In the embodiment of the present invention, the counter 92 calculates the latch signal S according to the first clock signal CLK1 L Number of pulses N C. After the duration of a predetermined number of pulses in each first clock signal CLK1, the counter 92 will be reset and then the number N will be recalculated C. The aforementioned predetermined number is a positive integer, and the duration of the predetermined number of pulses in the first clock signal CLK1 is equal to the aforementioned predetermined period. When the latch signal S L When it is at a high level and the rising edge of the first clock signal CLK1 is detected, the number of pulses calculated by the counter 92 will increase by one.

[0088] The control circuit 60a also includes a logic operator 94. The logic operator 94 is based on the first phase signal Second phase signal And latch signal S L To generate the third phase signal And the fourth phase signal In detail, when the latch signal S L At high level, and the first phase signal At high level, the third phase signal It is at high level. When the latch signal S L At high level, and the second phase signal At high level, the fourth phase signal It is also at high level.

[0089] The control circuit 60a can be based on the latch signal S L From capacitance C 1 To C N Choose a capacitor with a suitable capacitance value to replace the first capacitor Ca. On the one hand, if every time the rising edge of the first clock signal CLK1 is detected, the latch signal S L Are at a high level, indicating that the capacitance value of the panel capacitor Cp may be greater than or equal to (Ca+Cb), and the control circuit 60a can be changed from the capacitor C 1 To C N Choose another capacitor with a larger capacitance value to replace the original first capacitor Ca. On the other hand, if every time the rising edge of the first clock signal CLK1 is detected, the latch signal S L Are at low level, indicating that the capacitance value of the panel capacitor Cp may be less than or equal to Ca, and the control circuit 60a can be changed from the capacitor C 1 To C N Choose another capacitor with a smaller capacitance value to replace the original first capacitor Ca.

[0090] The control circuit 60a also includes a signal processor 96. The signal processor 96 depends on the number N C One capacitor is selected from the plurality of capacitors as the first capacitor Ca. For example, if the number N C Equal to the aforementioned predetermined number, which means that each time the rising edge of the first clock signal CLK1 is detected within the aforementioned predetermined period, the latch signal S L Are at high level, which can make the control circuit 60a from the capacitor C 1 To C N Choose another capacitor with a higher capacitance value to replace the original first capacitor Ca. For example, when the capacitance value of the panel capacitor Cp is 21.25 pF, which is greater than the sum of the capacitance values ​​of the first capacitor Ca (20 pF) and the second capacitor Cb (1 pF), N C Will be equal to a predetermined number, so that the signal processor 96 of the control circuit 60a can be switched from the capacitor C 1 To C N Choose another capacitor with a capacitance of 21pF to replace the original capacitor Ca. Furthermore, if the number NC is zero, it means that every time the rising edge of the first clock signal CLK1 is detected in the aforementioned predetermined period, the latch signal S L Are at a low level, so that the control circuit 60a from the capacitor C 1 To C N Choose another capacitor with a smaller capacitance value to replace the original first capacitor Ca. For example, when the capacitance value of the panel capacitance Cp is 19.5pF, it is smaller than the first capacitance Ca(20pF), N C Will be equal to zero, so that the signal processor 96 of the control circuit 60a can be changed from the capacitor C 1 To C N Choose another capacitor with a capacitance of 19pF to replace the original capacitor Ca.

[0091] In this example Image 6 As mentioned, the capacitance value of the panel capacitance Cp in the touch panel 100a can also be determined according to equation (3). Figure 7 to Figure 9 It is a signal timing diagram of the touch panel 100a, where the capacitance values ​​of the panel capacitor Cp are 20.5pF, 20.75pF and 20.25pF respectively.

[0092] Picture 10 It is a functional block diagram of the touch panel 100b according to an embodiment of the invention. The touch panel 100b is similar to the touch panel 100a. The touch panel 100b also includes a panel capacitor Cp, a first capacitor Ca, a second capacitor Cb, a first clock phase generator 22, six switches SW1-SW6 and a control circuit 60a. The connection relationship between the panel capacitance Cp, the first capacitance Ca, the second capacitance Cb, the first clock phase generator 22 and the six switches SW1-SW6 in the touch panel 100b and their functions are related to the panel capacitance Cp, the first A capacitor Ca, a second capacitor Cb, and the first clock phase generator 22 are the same as the six switches SW1-SW6. The main difference between the touch panel 100 a and the touch panel 100 b is that the touch panel 100 b further includes a second clock phase generator 24. The second clock phase generator 24 generates a fifth phase signal according to a second clock signal CLK2 And the sixth phase signal When the fifth phase signal In the first state (for example: high voltage state), the sixth phase signal It is in the second state (for example: low voltage state). When the sixth phase signal When in the first state, the fifth phase signal It is in the second state. The logic operator 94 is based on the fifth phase signal Sixth phase signal And latch signal S L To generate the third phase signal And the fourth phase signal In this embodiment, the frequency of the second clock signal CLK2 is N times the frequency of the first clock signal CLK1, where N is an integer. For example, when N is equal to 2, the signal timing diagram of the touch panel 100b is as follows Picture 11 Shown.

[0093] The second capacitor Cb is also used to compensate the voltage level V O The voltage difference with the third reference voltage VR3. Since the fifth switch SW5 and the sixth switch SW6 are based on the third phase signal And the fourth phase signal And turn on successively, the second capacitor Cb is charged and discharged at an appropriate time, so that the voltage level V O It oscillates near the third reference voltage VR3.

[0094] When the integral signal S i When greater than the third reference voltage VR3, the signal S is amplified OP At high level. When the integral signal S i When less than the third reference voltage VR3, amplify the signal S OP It is at high level. The latch circuit 90 also temporarily stores the large signal S according to the first clock signal CLK1 OP To output the latch signal S L To the logical operator 94. In detail, when the signal S is amplified OP When the signal is at high level and the rising edge of the first clock signal CLK1 is detected, the signal S is latched L Will be pulled to high level. Moreover, when the signal S is amplified OP When the signal is at low level and the rising edge of the first clock signal CLK1 is detected, the signal S is latched L Will be pulled to low level. The counter 92 calculates the latch signal S according to the first clock signal CLK1 in a predetermined period L The number of clocks.

[0095] Only when the latch signal S L And the fifth phase signal When both are at high level, the third phase signal The voltage level can be high. Only when the latch signal S L And the sixth phase signal When both are at high level, the fourth phase signal The voltage level can be high. When the third phase signal When it is high, the fifth switch SW5 can be turned on. And when the sixth phase signal When it is high, the sixth switch SW6 can be turned on. Therefore, the second capacitor Cb is periodically charged and discharged.

[0096] In summary, the fifth switch and the sixth switch will be turned on/off at an appropriate time. Therefore, the capacitance difference between the panel capacitor and the first capacitor will be accurately determined according to the capacitance value of the second capacitor and the number of clocks to latch the signal in a predetermined period.

[0097] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is subject to the claims of the present invention.

[0098] This application claims the priority of provisional application No. 61219771 filed in the United States on June 24, 2009. The entire contents of the above-mentioned patent applications are incorporated herein by reference to become a part of this specification.