Method for simulating radio frequency metal oxide semiconductor (MOS) varactor

Abstract

The invention discloses a method for simulating a radio frequency metal oxide semiconductor (MOS) varactor, which comprises the following steps of: establishing a radio frequency MOS varactor simulation model, simulating the radio frequency MOS varactor by utilizing the radio frequency MOS varactor simulation model, and simulating the characteristic that the capacitor of the radio frequency MOS varactor is changed along with voltage changes. A model of a variable capacitor in a topological structure of the radio frequency MOS varactor simulation model is simulated by an MOS device model of the same type; and the gate of the MOS device model of the same type is one end of the variable capacitor, the source and drain of the MOS device model of the same type are connected in parallel to formthe other end of the variable capacitor, and the body end of the MOS device model of the same type is grounded. By the method for simulating the radio frequency MOS varactor, the condition of non-convergence in simulation is avoided, simultaneously uniform scaling is realized, the extendibility of the model is effectively achieved, the modeling complexity of the radio frequency MOS varactor is reduced, and a radio frequency integrated circuit can be conveniently designed.

Description

technical field [0001] The invention relates to semiconductor design technology, in particular to a simulation method of a radio frequency MOS varactor. Background technique [0002] MOS varactor (variable capacitor) is one of the important components of RF CMOS or BiCMOS integrated circuits, and is widely used in RF circuit modules such as voltage-controlled oscillators. The cross-sectional view of the traditional N-type MOS varactor (variable container) is shown in figure 1 : In the figure, Lg is gate parasitic inductance, Rg is gate parasitic resistance, C_MOS is MOS capacitance, Rnw is channel region resistance, Rnwe is N+ injection region parasitic resistance, Rs is source / drain parasitic resistance, Ls is source / drain The parasitic inductance of the drain terminal, Cfr is the capacitance of the overlapping part of the gate and the source-drain N+ region, Dnwi and Dnwe are the parasitic diodes of the P-type substrate and the N-well, Rsub is the parasitic resistance of ...

AI Technical Summary

Problems solved by technology

Models using empirical formulas are not easy to achieve proportional scaling of the model, and the scalability is poor; for N-type MOS varactors, PMOS device models are used, or for P-type MOS varactors, NMOS device models are used. Two high-value resistors are connected at both ends of the source and drain to simulate the floating state of the source and drain, which is easy to cause non-convergence in the circuit simulation process

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