High dynamic strapdown inertial navigation parallel computing device
A strapdown inertial navigation and parallel computing technology, applied in directions such as navigation through velocity/acceleration measurement, can solve problems such as difficulty in increasing the calculation rate of navigation solutions, and difficulty in ensuring system real-time performance, so as to improve navigation accuracy and enhance flexibility. , the effect of reducing costs
Inactive Publication Date: 2012-05-23
ZHEJIANG UNIV
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Problems solved by technology
The serial calculation feature of DSP makes it difficult to increase the calculation rate of navigation solution, so it is difficult to ensure the real-time performance of the system in a highly dynamic environment
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[0025] The general principle diagram of the strapdown inertial navigation parallel computing device of the present invention is as follows: figure 1 As shown, the parallel computing device consists of an FPGA chip, a power supply circuit, a configuration circuit, a signal acquisition circuit and a signal output circuit, wherein the FPGA chip adopts the Virtex5 series FPGA of Xilinx company model XC5VSX95T. The general working process of the parallel computing device is as follows: the power supply circuit provides working power for the FPGA chip and the configuration circuit, the configuration circuit adopts the main serial mode, and when the FPGA is powered on, the configuration circuit automatically converts the off-chip non-volatile memory Platform Flash PROM to The configuration bit stream in is read into the static memory SRAM to realize the internal structure mapping. The fiber optic gyroscope, quartz flexible accelerometer and GPS receiver send the sensor signal to the ...
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The invention discloses a high dynamic strapdown inertial navigation parallel computing device, which consists of a field programmable gate array (FPGA) chip, a power supply circuit, a configuration circuit, a signal acquisition circuit and a signal output circuit, wherein the FPGA chip integrates a data acquisition module, an initial alignment module, a parallel navigation resolving module and acommunication module; the output signals of a fiber optic gyro, a quartz flexible accelerometer and a global position system (GPS) receiver are input into the data acquisition module of the FPGA chipthrough the signal acquisition circuit; the signals are pretreated and transmitted to the initial alignment module and the parallel navigation resolving module; the initial alignment module sends calculated initial values of navigation parameters to the parallel navigation resolving module, the navigation parameters are updated and calculated in the parallel navigation resolving module; the resolved navigation information is sent to the communication module; and the signals are sent to other equipment by the signal output circuit. The device disclosed by the invention greatly improves the computing speed of a strapdown inertial navigation system (SINS) resolving algorithm and improves the navigation precision of the SINS.
Description
technical field [0001] The invention relates to the field of strapdown inertial navigation, in particular to a single FPGA-based strapdown inertial navigation parallel computing device suitable for a high dynamic environment. Background technique [0002] In recent years, programmable logic device technology represented by FPGA has achieved rapid development. The latest FPGA device launched by Xilinx not only integrates abundant configurable logic block resources, but also contains a large number of DSP48(E) units for computing-intensive applications. Among them, the DSP48 (E) core can be used to realize efficient floating-point operation, and the abundant logic block resources can be used to realize large-scale parallel operation. It can be seen that in terms of hardware, FPGA has great advantages in the field of parallel computing. [0003] In a highly dynamic environment, the Strapdown Inertial Navigation System (SINS) needs to use a fast and high-precision navigation so...
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IPC IPC(8): G01C21/16
Inventor 马龙华孙国栋吴铁军
Owner ZHEJIANG UNIV