Method for realizing frequency fine-tuning of chip on parallel testing machine

Abstract

The invention discloses a method for realizing the frequency fine-tuning of chips on a parallel testing machine, comprising the following steps of: merging a pre-gear writing correction data vector and a next-gear reading time vector into a test vector to obtain a plurality of test vectors in a program of the parallel testing machine; then sequentially executing the plurality of test vectors by the parallel testing machine, and continuously circularly executing till all the tested chips of a simultaneously tested object set are ineffective and eliminated or till circulation is finished; and finally activating chip correction data lastly written into the tested chips which are in a passable state and are connected with test channels which correspond to a hardware register, wherein clock period fine tuning circuits of the tested chips carry out fine tuning on clock periods according to the lastly written chip correction data. The invention can simultaneously test the frequency of multiple chips.

Description

technical field [0001] The invention relates to chip testing, in particular to a method for realizing chip frequency fine-tuning on a parallel testing machine. Background technique [0002] Current parallel testing machines such as figure 1 As shown, a vector module of the tester sends test vectors to multiple chips for simultaneous testing. When a chip fails, the system will automatically reject these chips and disconnect these chips. However, the current parallel testing machine (such as T5335) has no modules for frequency testing and cannot perform frequency testing on chips. [0003] However, in the existing testing machines capable of frequency testing, the frequency testing module can automatically count the number of times the clock signal level of the chip under test changes. The clock signal frequency of the tested chip is tested, but because the clock signals of different chips will not be synchronized, and the frequency is not consistent, one frequency test modu...

AI Technical Summary

Problems solved by technology

However, the current parallel test machine (such as T5335) has no frequency test module and cannot perform frequency test on the chip

[0003] However, in the existing testing machines capable of frequency testing, the frequency testing module can automatically count the number of times the clock signal level of the chip under test changes. The clock signal frequency of the tested chip is tested, but because the clock signals of different chips will not be synchronized, and the frequency is not consistent, one frequency test module cannot test the clock signal frequency of multiple chips at the same time, and does not have parallel test function , it is impossible to test and fine-tune the frequency of different chips at the same time. Generally, it is necessary to test each chip to different frequencies, and then write different correction data to each chip under test according to different frequency values. The above process cannot realize multi-chip simultaneous testing. , the test time will be relatively long, and the requirements for the hardware of the device are relatively high

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