Grid-control schottky junction field effect transistor with tunneling dielectric layer and formation method

Abstract

The invention provides a grid-control schottky junction field effect transistor with a tunneling dielectric layer. The transistor comprises a substrate, a channel region, a metal source region, the tunneling dielectric layer, a drain region and a grid stack, wherein the channel region is formed in the substrate and is a first semiconductor material, the metal source region is formed in the substrate and is adjacent to one end of the channel region, the tunneling dielectric layer is formed between the metal source region and the channel region, a metal-dielectric-semiconductor tunnel junction is formed by the metal source region, the tunneling dielectric layer and the channel region and has rectification characteristic, the drain region is formed in the substrate and is adjacent to the other end of the channel region, the drain region is a second semiconductor material, and the grid stack is formed on the channel region. The basic operating principle of the semiconductor structure provided by the invention is that the high-speed switching between a schottky junction and a tunnel junction can be realized through the conversion of the grid voltage; therefore, the transistor has more excellent switching characteristic and high-frequency characteristic.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a gate-controlled Schottky junction field effect transistor with a tunnel dielectric layer and a forming method. Background technique [0002] For a long time, in order to obtain higher chip density, faster working speed and lower power consumption, the feature size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been continuously scaled down. Micro and nano scale range. However, a serious challenge that comes with it is the emergence of short-channel effects, such as subthreshold voltage drops (V t Roll-off), drain-induced barrier lowering (DIBL), source-drain punch through (punch through) and other effects, make the sub-threshold slope of MOSFET devices worse, and the off-state leakage current increases significantly, resulting in performance deterioration . [0003] TFET (Tunneling Field Effect Transistor, Tunneling Field Effe...

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Problems solved by technology

[0006] The purpose of the present invention is to at least solve one of the above-mentioned technical defects, especially to solve the complex process of TFET devices and the high defect of generating cost

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