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Static phase interpolator and clock and data recovery (CDR) circuits employing the same

A static phase and interpolator technology, applied in phase shifters, networks using active components, pulse processing, etc., can solve the problem that static phase interpolators cannot provide linearity

Inactive Publication Date: 2011-10-05
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although, compared to phase interpolators based on current mode logic, image 3 The static phase interpolator is smaller in size and power consumption, but the static phase interpolator cannot provide good linearity

Method used

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  • Static phase interpolator and clock and data recovery (CDR) circuits employing the same
  • Static phase interpolator and clock and data recovery (CDR) circuits employing the same
  • Static phase interpolator and clock and data recovery (CDR) circuits employing the same

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Embodiment Construction

[0041] The description in the exemplary embodiments should be accompanied by the appended Figure 1 Read together, these attached figures should be considered part of the overall description. Relative terms are used for convenience of description and do not require that a device be operated or configured in a particular orientation. Terms of communicating, coupling, and the like, such as "connected" and "interconnected," mean that a feature communicates with another feature directly or indirectly through intervening means, unless specifically stated otherwise.

[0042] Figure 4 is a schematic circuit diagram of an exemplary embodiment of the static interposer 100 . Figure 5 is shown at Figure 4 Design of one of the switching cells in the static phase interpolator shown. Image 6 generally shown as image 3 and Figure 4 The timing diagram for the operation of the static phase interpolator is shown.

[0043] Please refer to Figure 4 , the static phase ...

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Abstract

Disclosed are a static phase interpolator and clock and data recovery (CDR) circuits employing the same. The static phase interpolator includes first and second inverters coupled in parallel between an output node and first and second input nodes for receiving first and second clock signals, first and second switch elements coupled to the first and second inverters for selectively turning on individual ones of the inverters in response to a phase control signal, and a third inverter coupled the output node. The interpolator may include a slew rate controller coupled to the first and second input nodes. Also, each inverter of the interpolator may include a PMOS transistor in series with an NMOS transistor and have a respective one of the switch elements disposed between the PMOS and NMOS transistors.

Description

technical field [0001] The present invention relates generally to a phase interpolator, and more particularly to a static phase interpolator for use in clock and data recovery circuits. Background technique [0002] The phase interpolator is used in a clock and data recovery circuit to generate clock signals with different phases and select a clock signal with a suitable phase. Given two phase inputs (eg, out-of-phase signals by 90 degrees), a phase interpolator provides an output with a phase between the two input phases. [0003] figure 1 It is a block diagram showing the clock and data recovery circuit 10 . The clock and data recovery circuit 10 includes a phase interpolator 15 that receives a pair of signals CLKP and CLKN with different phases. The output of the phase interpolator 15 is coupled to a sense amplifier flip flop (sense amplifier flip flop; SAFF) or selectively coupled to a latch (together labeled sense amplifier flip flop / latch 20), The sense amplifier f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/15H03H17/02
CPCH03H11/265H03K2005/00286
Inventor 傅敬铭
Owner TAIWAN SEMICON MFG CO LTD