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A non-iterative ldpc code decoder

An LDPC code, non-iterative technology, applied in the field of channel error correction code decoding, can solve the problems that the check node update and variable node update cannot be performed at the same time, and the decoding operation speed is slow, achieving strong real-time performance and simple control unit , good versatility

Inactive Publication Date: 2011-12-28
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0023] like figure 1 As shown, the check node update and variable node update of the traditional iterative LDPC code decoder cannot be performed at the same time. Therefore, the check node update unit CNU and the variable node update unit VNU of this decoder are both Only half of the time is working, and the rest of the time is idle, and the decoding operation speed is slow

Method used

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  • A non-iterative ldpc code decoder
  • A non-iterative ldpc code decoder
  • A non-iterative ldpc code decoder

Examples

Experimental program
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Embodiment

[0058] figure 2 It is a functional block diagram of a specific embodiment of a non-iterative LDPC code decoder in the present invention.

[0059] In this example, if figure 2 As shown, the LDPC code decoder of the present invention includes: initial likelihood ratio information memory La_0, Lb_0, k-level arithmetic unit, decision and output module D and control unit;

[0060] The first-level operation unit includes two first-level variable node information matrix memories Qa_1, Qb_1, one-level check node update unit CNU_1, two first-level likelihood ratio information memories La_1, Lb_1, and two first-level check node information matrix memories Ra_1, Rb_1, primary variable node update unit VNU_1.

[0061] The composition of the second-level computing unit is the same as that of the same-level computing unit, including two secondary variable node information matrix memories Qa_2, Qb_2, two secondary check node update units CNU_2, secondary likelihood ratio information memo...

example

[0105] In this example, the check matrix of the LDPC code has the following structure, and the non-iterative LDPC code decoder of the present invention has two stages, namely:

[0106] H = 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 ...

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Abstract

The invention discloses a non-iterative type LDPC code decoder which comprises: two initial likelihood ratio information storages, a k grade operation unit, a judgment and output module D and a control unit. Under control of the control unit, a LLR value of a LDPC frame to be decoded is alternatively stored into the two initial likelihood ratio information storages. Simultaneously, variable node information matrix initialization is alternatively carried out and is stored in two variable node information matrix storages in a level-one operation unit. A verification node update unit and a variable node update unit interlacedly and alternatively read, process and store data. A utilization rate is 100%. In the traditional LDPC code decoder, the utilization rate of the operation unit is not high. The non-iterative type LDPC code decoder of the invention solves the above problem. Finally, through multiple cascaded operation processing, an obtained recovery information bit sequence is directly determined. A plurality of operation unit cascades substitute a traditional iterative operation. A pipeline operation can be completely realized. Therefore, a decoding operation speed is high.

Description

technical field [0001] The invention belongs to the technical field of channel error correction code decoding, and more specifically relates to a non-iterative LDPC code decoder. Background technique [0002] LDPC code is a special linear block code whose parity check matrix is ​​sparse. With its excellent decoding performance, LDPC codes are widely used as forward error correction (FEC) in various communication systems. [0003] The decoding algorithm of LDPC codes is relatively complicated, and the classic algorithms include sum-product algorithm and minimum-sum algorithm. Due to the higher complexity of the sum-product algorithm, the decoding performance of the minimum-sum algorithm has a small gap with the former, but the hardware complexity of the decoder is much lower than that of the sum-product algorithm, and the hardware pipeline is easier to implement than the sum-product algorithm. Therefore, most LDPC decoders will use the minimum-sum algorithm, which is implem...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 王斯维许渤邱昆
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA