Sense amplifier enable signal generation device, method, and system

Abstract

Device, system and method for generating a sense amplifier enable ("SAE") signal having a programmable delay with a feedback loop to control the SAE signal duty cycle, which can be used in SRAM or DRAM, or other kinds of memory cells. An illustrative non-limiting embodiment comprises: a programmable clock chopper, a low pass filter, a bias generator, a comparator, and a feedback control module.

Description

technical field [0001] The present invention generally relates to an apparatus and method for semiconductor memory devices, and more particularly to a method for generating a sense amplifier enable (Sense Amplifier Enable; SAE) signal with a programmable delay (Programmable Delay). devices and methods. Background technique [0002] Various types of memory components such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM) components store information in memory cells (Memory Cells), wherein The memory cells are arranged in an array of selectable rows and columns. The lines connecting each row are generally called word lines (Word Lines; WL). Each column usually includes a bit line (Bit Line) and its complementary (Complement) bit line. Start WL to select the storage unit to be stored. The data stored by each memory cell is transmitted to the sense amplifier circuit system for amplification through the bit line. [0003] SA is driven by an enablin...

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Problems solved by technology

A solution is also needed to eliminate the internal self-reset path in known self-timed methods, so that the resulting SAE signal can be more tolerant to PVT variation, a

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