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Multiphase multimode frequency-dividing circuit with small frequency coefficient

A multi-mode frequency division and frequency division coefficient technology, which is applied in the direction of electrical components, pulse counters, counting chain pulse counters, etc., can solve the problem of low frequency division coefficient of the clock frequency multiplication system, achieve short feedback path, simple structure, and improved The effect of operating frequency

Active Publication Date: 2015-02-04
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in this application system, the low frequency division factor of the clock frequency multiplication system is a special system requirement, which puts forward new requirements for the clock frequency multiplication system with spread spectrum function

Method used

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  • Multiphase multimode frequency-dividing circuit with small frequency coefficient
  • Multiphase multimode frequency-dividing circuit with small frequency coefficient
  • Multiphase multimode frequency-dividing circuit with small frequency coefficient

Examples

Experimental program
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Effect test

Embodiment 1

[0022] figure 1 It is a structural schematic diagram of the multi-phase multi-mode frequency division circuit of the present invention. Such as figure 1 As shown, the multi-phase multi-mode frequency division circuit of the present invention includes two control terminals and four D flip-flops, wherein,

[0023] The "NAND" logic signal of the output signals Q3 and Q4 of the third D flip-flop D3 and the fourth D flip-flop D4 is used as the input signal of the D terminal of the first D flip-flop D1;

[0024] The logic AND of the control signal k1 of the first control terminal and the output signal Q3 of the third D flip-flop D3 and the logic AND of the output signal Q1 of the first D flip-flop D1 are used as the second D flip-flop D2 The input signal of the D terminal;

[0025] The output signal Q2 of the second D flip-flop D2 is used as the input signal of the D terminal of the third D flip-flop D3;

[0026] The logic NOT of the output signal Q3 of the third D flip-flop D3 ...

Embodiment 2

[0048] The structure of the multi-phase multi-mode frequency division circuit provided in this embodiment is similar to the structure of the multi-phase multi-mode frequency division circuit in Embodiment 1, the only difference is that figure 1 The specific implementation of the AND gate and the second D flip-flop D2 in the shown multi-phase multi-mode frequency division circuit has been improved.

[0049] The polyphase multimode frequency division circuit provided by Embodiment 2 also includes two control terminals and four D flip-flops, wherein,

[0050] The AND gate is integrated in the second D flip-flop D2, which makes the input of the D terminal of the second D flip-flop the "AND" logic, and this "AND" logic is compared with a single "D" terminal input, Both are only level 1, with no additional propagation delay;

[0051] The "NAND" logic signal of the output signal of the third D flip-flop D3 and the fourth D flip-flop D4 is used as the input signal of the D terminal o...

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Abstract

The invention discloses a multiphase multimode frequency-dividing circuit with a small frequency coefficient, comprising two control ends and four D triggers, wherein the NAND logical signals of the output signals of the third D trigger and the fourth D trigger are served as the input signals of the first D trigger; the NAND logical signals of the control signal of the first control end and the output signal of the third D trigger, and the logical AND of the output signal of the first D trigger are served as the input signals of the second D trigger; the output signal of the second D trigger is served as the input signal of the third D trigger; the logical NOT of the output signal of the third D trigger and the NAND logical signal of the control signal of the second control end are served as the input signal of the fourth D trigger; and the output signal of the first D trigger is served as the output signal of the multiphase multimode frequency-dividing circuit.

Description

technical field [0001] The invention relates to a frequency division circuit, in particular a multi-phase multi-mode frequency division circuit with a small frequency division coefficient is designed. Background technique [0002] Clock spread spectrum technology is an important way to reduce system EMI (Electromagnetic Interference). Currently, the commonly used frequency division circuits have relatively high frequency division coefficients, ranging from tens to thousands. The TFT-LCD (Thin Film Transistor-Liquid Crystal Display) display system also requires low system EMI. In addition to adopting the system design method, the timing controller (TCON) chip with spread spectrum function in the TFT-LCD display system is also used. An important solution. But in this application system, it is a special system requirement that the frequency division coefficient of the clock frequency multiplication system is very low, which puts forward new requirements for the clock frequency...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K23/66
Inventor 覃正才
Owner SHANGHAI BEILING