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IO (Input/Output) circuit for accurate pull-down current

A current pulling and circuit technology, applied in the field of IO circuits, can solve problems such as large deviation of the pull-down current I, inconformity with communication signals, long completion time of the pull-down current I establishment time, etc., and achieve the effect of improving accuracy and shortening start-up time

Active Publication Date: 2012-05-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of the existing IO circuit that can pull down the current is that the establishment time of the pull-down current I is relatively long, and the deviation of the pull-down current I is relatively large, which does not meet the requirements as a communication signal.

Method used

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  • IO (Input/Output) circuit for accurate pull-down current
  • IO (Input/Output) circuit for accurate pull-down current
  • IO (Input/Output) circuit for accurate pull-down current

Examples

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Embodiment Construction

[0019] like image 3 Shown is a schematic structural diagram of an IO circuit that can pull down a precise current according to an embodiment of the present invention. The IO circuit capable of pulling down precise current in the embodiment of the present invention includes: a first resistor R1 , an electrostatic protection circuit for power supply, an electrostatic protection circuit for ground, and a pull-down current functional module. The first end of the first resistor R1 is connected to the pad PAD, the second end of the first resistor R1 is connected to the internal circuit of the chip, and the first resistor R1 is used for current limiting during electrostatic protection. The electrostatic protection circuit for the power supply is connected between the power supply VDD and the first terminal of the first resistor R1. The ground electrostatic protection circuit is connected between the ground and the first end of the first resistor R1. The pull-down current function ...

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PUM

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Abstract

The invention discloses an IO (Input / Output) circuit for an accurate pull-down current. The IO circuit comprises a pull-down current functional module which comprises an operational amplifier, a second resistor, an NMOS (Negative Channel Metal Oxide Semiconductor) transistor and a switch module, wherein the second resistor, the NMOS transistor and the switch module are serially connected between a first resistor and the ground, an output end of the operational amplifier is connected with the grid electrode of the NMOS transistor, an anti-phase input end of the operational amplifier is connected with the second end of the second resistor, an in-phase input end of the operational amplifier is connected with a reference voltage, and the operational amplifier and the switch module are further connected with enable signals. When the enable signals are effective, the operational amplifier is formed in a negative feedback loop, the anti-phase input end of the operational amplifier is clamped to the reference voltage, the NMOS transistor is opened, the switch module is switched on, and the pull-down current is formed between the second end of the first resistor and the ground, wherein the size of the pull-down current is equal to the quotient of the reference voltage divided by the resistance of the second resistor. According to the IO circuit, the time for starting the pull-down current can be shortened, and the accuracy of the pull-down current is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to an IO circuit capable of pulling down precise current. Background technique [0002] like figure 1 As shown, it is a schematic structural diagram of an existing IO circuit without a pull-down current. The existing IO circuit without a pull-down current includes: a resistor R, an electrostatic protection circuit for a power supply, and an electrostatic protection circuit for a ground. The first end of the resistor R is connected to the pad PAD, the second end of the resistor R is connected to the internal circuit of the chip, and the resistor R is used for current limiting during electrostatic protection. The electrostatic protection circuit for the power supply is connected between the power supply VDD and the first end of the resistor R. The ground electrostatic protection circuit is connected between the ground and the first end of the resistor R. The existing IO circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0185
Inventor 骆川周平
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP