Non-volatile memory cell with non-ohmic selection layer

Abstract

A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.

Description

Background technique [0001] Solid state memory (SSM) often includes one or more arrays of individually programmable memory cells configured to store data by applying a write current to the cells to store a sequence of bits. The stored bits can then be read during a read operation by applying an appropriate sense current and sensing the voltage drop across these cells. [0002] Some SSM cell configurations use logic storage bits coupled to switching devices. In read and write operations, while the switching device allows selective access to the resistive sensing element, the resistive element can be programmed to different resistances to represent different bit states. [0003] The future trend is to provide SSM arrays with larger data capacity and smaller manufacturing process feature sizes. However, the physical requirements of many switching devices have made the realization of these components more difficult. In addition, because it is very close to other components and high p...

AI Technical Summary

Problems solved by technology

However, the physical requirements of many switching devices have made the realization of these components more difficult

Also, smaller feature sizes can introduce a high probability of error when reading and writing data due to the very close proximity to other components and the high programming currents often used in modern logic storage bits

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