Chip-scale latch-up over-current protection circuit independent of power supply module

Abstract

A chip-scale latch-up over-current protection circuit independent of a power supply module relates to the field of integrated circuits and comprises a heavy current switching module, an equal-proportion current detection module, a judgment module and a self-start module, wherein a power supply PAD is connected to a chip power management module through a heavy current switching module and further connected to a core circuit, and is connected to the heavy current switching module through the equal-proportion current detection module, the judgment module and the self-start module sequentially; and the chip power management module is connected with the self-start module. The chip-scale latch-up over-current protection circuit can be conveniently used on a chip independent of the power supply module, is safer and more reliable and has the characteristics of strong universality and low power consumption.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a chip-level latch-up (Latch-up) overcurrent protection circuit independent of a power module. Background technique [0002] Due to manufacturing difficulties, only NMOS devices were available in the first few generations of MOS processes. In fact, many early microprocessors and analog circuits were manufactured using the NMOS process, but their power consumption was quite large. Although CMOS devices require a large number of mask plates and manufacturing processes, the zero static power consumption of CMOS logic still promotes the arrival of the era of CMOS technology. However, there is a serious problem in CMOS circuits, which is the latch-up phenomenon. [0003] The latch-up phenomenon refers to that in the CMOS process, the parasitic pnp and npn bipolar transistors form a positive feedback loop. In the working voltage range of , the parasitic diode is fully turned on, ...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that the detection circuit is built inside the power regulation circuit, which is directly related to the structure adopted by the power regulation circuit. The versatility is not strong, and it is impossible for designers who use third-party power supply hard cores.

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