Unlock instant, AI-driven research and patent intelligence for your innovation.

SoC substrate and manufacturing method thereof

A manufacturing method and substrate technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing mechanical strength, performance impact, SoC substrate manufacturing process, etc., to improve mechanical strength, suppress Mutual crosstalk and solve the effect of low-resistance substrate crosstalk

Inactive Publication Date: 2012-10-03
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
View PDF2 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in a typical CMOS process, such as figure 1 As shown, due to the existence of the substrate crosstalk effect (as indicated by the arrow), as the operating frequency of the circuit continues to increase, when the frequency approaches or exceeds gigahertz (GHz), the high-frequency noise generating module 101 (such as the digital circuit part ) will be transmitted to the high-frequency noise-sensitive modules 102 (such as the RF front-end part) through the low-resistance substrate 100, and will have a great impact on the performance of these high-frequency noise-sensitive modules 102, which directly affects the single The stability and reliability of the chip system integrated wireless sensor network chip in the communication process, and the substrate crosstalk effect becomes more and more significant with the increase of frequency
[0006] In the existing SoC substrate manufacturing technology, the porous silicon substrate isolation structure is usually grown in the bulk silicon substrate to effectively solve the low-resistance substrate crosstalk and effectively suppress the crosstalk between different modules after system integration, but in this In the method, a silicon nitride isolation layer for isolating electrodes is generally formed before the oxide layer on the surface of the substrate and the growth of porous silicon in the substrate. The formation of the silicon nitride layer increases the process steps and flow, making the entire SoC substrate The bottom manufacturing process is not compatible with the standard CMOS process, and will have an impact on the stress of the SoC substrate, which will increase its mechanical strength

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SoC substrate and manufacturing method thereof
  • SoC substrate and manufacturing method thereof
  • SoC substrate and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] Such as figure 2 As shown, the present embodiment proposes a SoC substrate manufacturing method, comprising the following steps:

[0051] S201, providing an integrated silicon substrate, where the bulk silicon substrate includes a plurality of device regions and isolation regions between adjacent device regions;

[0052]S202, forming mutually isolated doped polysilicon electrodes on the top of the front surface of the bulk silicon substrate, the doped polysilicon electrodes are distributed in a local area of ​​the device region and a local area of ​​the isolation region;

[0053] S203, depositing an oxide layer on the doped polysilicon electrode and the front surface of the bulk silicon substrate;

[0054] S204, forming pads in the oxide layer that are one-to-one aligned with the doped polysilicon electrodes in the local area of ​​the device region;

[0055] S205, forming a passivation layer on the pad and the oxide layer to obtain a silicon wafer to be etched;

[0...

Embodiment 2

[0085] Please refer to Figure 6 , 7A , 7B, the present embodiment provides a SoC substrate manufacturing method, including the following steps:

[0086] S601, providing an integrated silicon substrate 700, the bulk silicon substrate 700 including a plurality of device regions I, III and an isolation region II between adjacent device regions I, III;

[0087] S602, forming a doped polysilicon electrode 701 located in a local area of ​​the isolation region II on the top of the front surface of the bulk silicon substrate 700;

[0088] S603, depositing an oxide layer 702 on the doped polysilicon electrode 701 and the front surface of the bulk silicon substrate 700;

[0089] S604, forming pads 703a, 703b located above the device regions I and III of the bulk silicon substrate 700 in the oxide layer 702;

[0090] S605, forming a passivation layer 704 on the pads 703a, 703b and the oxide layer 702 to obtain a silicon wafer to be etched;

[0091] S606, packaging the silicon wafer ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a SoC (System on Chip) substrate manufacturing method. A doped polysilicon electrode located in a local region of an isolation area is directly formed at the top of the front face of a bulk silicon substrate, and then, a corrosive liquid intrudes into the back of the bulk silicon substrate through the current passing through the doped polysilicon electrode, so that a porous silicon isolating structure extending from the back of the substrate to the isolation area is formed, use of a silicon nitride layer and influence of the silicon nitride layer on the mechanical stress of the substrate are avoided, and the manufacturing method can be completely compatible with the conventional standard CMOS (Complementary Metal Oxide Semiconductor) technology. The SoC substrate provided by the invention is of a structure mainly consisting of the bulk silicon and the porous silicon, so that the problem of crosstalk of a low-resistance substrate is solved effectively, the problem of crosstalk among different device regions after system integration is restrained effectively, and simultaneously, the mechanical strength of the substrate is improved based on the properties of the bulk silicon and the porous silicon, which are are similar to those of the silicon material.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an SoC substrate and a manufacturing method thereof. Background technique [0002] With the continuous deepening of the research on wireless sensor network chips in the industry and academia, people have begun to not be satisfied with only realizing the functions of wireless sensor network chips, but have put forward more and more demands on the cost, volume, packaging and integration of chips. more urgent requirements. Based on these considerations, the concept of SoC (system-on-chip) system chip has been more and more commonly used in the research and development of wireless sensor network chips, and has increasingly become the mainstream trend of chip design. SoC refers to a product, which is an integrated circuit with a dedicated purpose, which contains a complete system and has all the content of embedded software. SoC is also called "system chip integration", wh...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/76H01L21/306
Inventor 李琛
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT