SoC substrate and manufacturing method thereof
A manufacturing method and substrate technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing mechanical strength, performance impact, SoC substrate manufacturing process, etc., to improve mechanical strength, suppress Mutual crosstalk and solve the effect of low-resistance substrate crosstalk
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Embodiment 1
[0050] Such as figure 2 As shown, the present embodiment proposes a SoC substrate manufacturing method, comprising the following steps:
[0051] S201, providing an integrated silicon substrate, where the bulk silicon substrate includes a plurality of device regions and isolation regions between adjacent device regions;
[0052]S202, forming mutually isolated doped polysilicon electrodes on the top of the front surface of the bulk silicon substrate, the doped polysilicon electrodes are distributed in a local area of the device region and a local area of the isolation region;
[0053] S203, depositing an oxide layer on the doped polysilicon electrode and the front surface of the bulk silicon substrate;
[0054] S204, forming pads in the oxide layer that are one-to-one aligned with the doped polysilicon electrodes in the local area of the device region;
[0055] S205, forming a passivation layer on the pad and the oxide layer to obtain a silicon wafer to be etched;
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Embodiment 2
[0085] Please refer to Figure 6 , 7A , 7B, the present embodiment provides a SoC substrate manufacturing method, including the following steps:
[0086] S601, providing an integrated silicon substrate 700, the bulk silicon substrate 700 including a plurality of device regions I, III and an isolation region II between adjacent device regions I, III;
[0087] S602, forming a doped polysilicon electrode 701 located in a local area of the isolation region II on the top of the front surface of the bulk silicon substrate 700;
[0088] S603, depositing an oxide layer 702 on the doped polysilicon electrode 701 and the front surface of the bulk silicon substrate 700;
[0089] S604, forming pads 703a, 703b located above the device regions I and III of the bulk silicon substrate 700 in the oxide layer 702;
[0090] S605, forming a passivation layer 704 on the pads 703a, 703b and the oxide layer 702 to obtain a silicon wafer to be etched;
[0091] S606, packaging the silicon wafer ...
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