Method of fabricating a plurality of gate structures

Abstract

The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.

Description

technical field [0001] The present invention relates to the fabrication of integrated circuits, and more particularly to a semiconductor device with multiple gate structures. Background technique [0002] As transistor dimensions decrease, gate oxide thickness must be reduced to maintain performance while gate lengths are shortened. However, in order to reduce gate leakage, a gate oxide layer with a high dielectric constant (high-k) is generally used, which allows a larger physical thickness and at the same time The same effective thickness as provided by using common gate oxides in future technology nodes is preserved. [0003] In addition, as technology nodes shrink, metal gate electrodes need to be used in the design of some integrated circuits (ICs) instead of common polysilicon gate electrodes, so as to improve device performance while reducing component sizes. The process of forming the metal gate electrode is referred to as a "gate last" process, in which the final ...

AI Technical Summary

Problems solved by technology

For example, in the "gate last" manufacturing process, due to the creation of undesired grooves in the interlayer dielectric (ILD) layer after the wet etch / dry etch of the dummy gate, between adjacent transistors Difficult to achieve ideal isolation

These grooves present in the ILD layer become receptacles for the metal in subsequent processes, increasing the possibility of electrical shorts and / or device failure

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