Dual damascene structure and formation method thereof as well as semiconductor device
A dual damascene structure, semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of reduced device service life and reduced time breakdown characteristics of dielectric layers.
Active Publication Date: 2012-10-31
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0007] The problem solved by the present invention is the double damascene structure of the prior art, the time breakdown characteristic (TDDB) of the dielectric layer is reduced, and the service life of the device is reduced
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[0034] In order to solve the technical problem that the formation method of the dual damascene structure in the prior art would reduce the time-dependent breakdown characteristics of the dielectric layer and reduce the performance of the semiconductor device, the inventors found that because the top surface of the plug in the prior art is round If the top surface of the plug is changed to an ellipse, and the major axis of the ellipse is along the extension direction of the interconnection line, and the short axis is perpendicular to the extension direction of the interconnection line, when a dual mosaic structure is formed, the plug on the oval top surface Due to the reduction of the length of the minor axis, the corresponding offset in the minor axis direction is correspondingly reduced, which can improve the time-dependent breakdown characteristics of the dielectric layer and improve the performance of the semiconductor device.
[0035] In the method of the dual damascene str...
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The invention discloses a dual damascene structure and a formation method thereof, as well as a semiconductor device. The formation method of the dual damascene structure comprises the steps as follows: a semiconductor substrate is provided; a device structure is formed in the semiconductor substrate; a dielectric layer is formed on the semiconductor substrate; a hard mask layer provided with a first opening is formed on the dielectric layer; the first opening defines a position of an interconnection trench; a photoresist layer provided with a second opening is formed on the hard mask layer, and the second opening defines a position of a through hole; the diameter of the second opening in the length direction of the first opening is larger than the diameter of the second opening in the width direction of the first opening; a third opening is formed by taking the photoresist layer as a mask and etching the dielectric layer; the photoresist layer is removed; the dielectric layer around the third opening is etched by taking the hard mask layer as the mask to form the interconnection trench and the through hole; conducting materials are filled in the through hole and the interconnection trench to form the dual damascene structure; and the diameter of a plug in the length direction of an interconnection line is larger than the diameter of the plug in the width direction of the interconnection line. According to the invention, the time dependent breakdown characteristic of the dielectric layer can be improved.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a double damascene structure, a forming method thereof, and a semiconductor device. Background technique [0002] The RC delay of the copper interconnection structure is smaller than that of the aluminum interconnection structure. In semiconductor devices, in order to reduce the RC (resistance capacitance delay) delay and improve the performance of semiconductor devices, the copper interconnection structure gradually replaces the aluminum interconnection structure. The formed copper interconnection structure is a dual damascene structure, and its formation method is a traditional dual damascene method. [0003] In the prior art, the method for forming a dual damascene structure is: [0004] refer to figure 1 , provide a semiconductor substrate 10, a device structure may be formed in the semiconductor substrate 10, and a dielectric layer 11 is formed on the semiconductor ...
Claims
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Login to View More IPC IPC(8): H01L21/768H01L23/522H01L23/528
Inventor 张海洋周俊卿
Owner SEMICON MFG INT (SHANGHAI) CORP