Semiconductor device

Abstract

Provided is a semiconductor device having a memory cell array structure capable of maintaining data efficiency and reducing power consumption. The semiconductor device comprises: a memory cell array including a plurality of memory array basic units (11), each including a plurality of memory cells for write and read; a first bus provided common to said plurality of memory array basic units, said first bus allowing transfer of address / control signals thereon, said first bus including at least one first buffer circuit (13A) that operates as a pipeline / register; a second bus (RWBS) provided common to said plurality of memory array basic units, said second bus allowing transfer of write / read data thereon, said second bus including at least one second buffer circuit (13B) that operates as a pipeline / register; a first control circuit (6) that sends said address / control signals on said first bus from one end thereof, sequentially in a sequence of from said memory array basic unit located at a remote end side with respect to said one end of said first bus, to said memory array basic unit at a near end side with respect to said one end of said first bus; and a second control circuit (7) that sends data signals on said second bus from one end thereof, sequentially in a sequence of from said memory array basic unit located at a remote end side with respect to said one end of said second bus to said memory array basic unit at a near end side with respect to said one end of said second bus, said write data transferred from said second bus to each of said memory array basic units being written in each of said memory array basic units, read data from a plurality of said memory array basic units being transferred on said second bus to get to said second control circuit, in a sequence of from said memory array basic unit located at said near end side with respect to said one end of said second bus to said memory array basic unit located at said remote end side with respect to said one end of said second bus, said second control circuit outputting said arrived read data.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a memory cell array. Background technique [0002] In recent years, in semiconductor memories such as DRAM (Dynamic Random Access Memory, dynamic random access memory), high-performance, high-speed operation, and large-capacity have been continuously developed, and due to DDR (Double Data Rate, double data rate) / The introduction of a structure such as DDR2 / DDR3 significantly increases the data bandwidth of the input and output of the memory. [0003] In order to improve the data bandwidth of the input and output of the memory, the READ (read) and WRITE (write) cycle (tRC: ROW CYCLE TIME) of the memory is improved, and the number of simultaneous operations (parallel number) inside the memory is improved (data The multi-parallelization of lines (IO lines) (increasing the number of parallels), the multi-blocking of memory arrays) lead to ...

AI Technical Summary

Problems solved by technology

[0057] However, if only the average latency is shortened, the memory access cycle itself is not shortened

Also, insufficient in cutting power

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