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Back-side contact formation

A back-contact and front-contact technology, applied in electrical components, electrical solid-state devices, circuits, etc., can solve the problems of die layout increasing production complexity and cost

Active Publication Date: 2015-03-25
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, manufacturing different die layouts for different packages and / or applications increases production complexity and cost

Method used

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  • Back-side contact formation
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Embodiment Construction

[0013] Although the present disclosure can be modified into various modifications and alternative forms, examples of the present disclosure are shown by way of example in the drawings and will be described in detail. It should be understood, however, that the disclosure is not intended to be limited to the particular embodiments shown and / or described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.

[0014] In one or more embodiments, a semiconductor die is provided that can be easily reconfigured by post-manufacturing processes to enable backside contacts. This capability allows a batch of the same semiconductor die to be used in a greater variety of applications. Some dies may be used in packages using front contact pads, while others may be used in packages using back contacts. Since this increases versatility and simplifies manufacturing, manufacturing costs can be reduced...

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Abstract

In one embodiment, a semiconductor is provided comprising a substrate (202) and a plurality of wiring layers (302) and dielectric layers (304) formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer (402) is formed on the plurality of wiring layers. A first contact pad (404) is formed in the passivation layer and electrically coupled to the circuit. A wire (610) is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) (502) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Description

technical field [0001] The present invention relates to semiconductors and methods of forming them. Background technique [0002] One of the major trends in the semiconductor packaging industry is the use of surface mount technology (SMT) as an alternative to traditional plated-through-hole (PTH) technology. Compared with PTH technology, SMT technology offers various advantages, such as higher packing density, higher pin count and shorter interconnection length and easier automation. Since SMT requires electronics and components to be mounted on the surface of a printed circuit board (PCB) or substrate, the materials and structures of traditional through-hole components, including capacitors, resistors, and inductors, must be redesigned to meet Today's demand for short, thin, light and small electronic devices. Examples of semiconductor devices meeting these goals include quad-flat (non-leaded packages). The quad flat no-lead package has a package structure in which space...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/522H01L23/538H01L21/768
CPCH01L24/05H01L2224/0557H01L23/481H01L21/76898H01L24/03H01L2224/06181H01L24/06H01L2924/00014H01L2224/02372H01L2224/05548H01L2224/05552
Inventor 弗洛里安·施密特迈克尔·齐恩曼
Owner NXP BV
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