Pipeline read-write method of direct memory access (DMA) structure based on high-speed serial bus

Abstract

The invention discloses a pipeline read-write method of a direct memory access (DMA) structure based on a high-speed serial bus. A mainframe is provided with a DMA register through a digital conversion receiver (DCR). A TX (transmission) state machine sequentially and cyclically transmits requests of descriptor reading, data reading and descriptor writing according to settings, and then the various requests are controlled by a port state machine to be finished. The port state machine transmits reading or writing operation through a laboratory information system (LIS) bus and transmits a plurality of descriptor reading and data reading operation to be processed through the LIS bus. The LIS bus sequentially transmits a plurality of reading requests and then sequentially receives data. The port state machine respectively updates received data into a register file or transmits the received data to a streamLink interface. Meanwhile, an RX (receiving) state machine sequentially and cyclically transmits the requests of the descriptor reading, the data reading and the descriptor writing according to the settings, and then the various requests are controlled by the port state machine to be finished. The port state machine transmits the reading or the writing operation through the LIS bus.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a pipeline reading and writing method based on a DMA structure of a high-speed serial bus for reading memory data. Background technique [0002] At present, with the development of computer technology, the bus has also developed from a parallel bus to a high-speed serial bus. The read and write bandwidth of the bus has reached more than 1GB / s, and the read and write of large amounts of data is mostly handled by DMA, so the DMA working mode and the way of reading and writing will directly affect the utilization rate of the bus bandwidth. [0003] Existing DMAs are mostly designed for parallel buses, which are only suitable for reading and writing on parallel buses. If it is applied to a high-speed serial bus, it will greatly affect the read and write efficiency, and the high bandwidth of the high-speed serial bus cannot be utilized. Taking the reading process of the bus as an e...

AI Technical Summary

Problems solved by technology

The response speed of the parallel bus is very fast, only a few clocks, and the read request is responded within 100ns, but the transmission data is relatively slow

For the high-speed serial bus, due to the large bus delay, the response to the read request is very slow, above 1us, but the data transmission is relatively fast

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