dfn package structure of power mosfet chip

Abstract

The invention discloses a dual flat package (DFN) structure of a power metal-oxide-semiconductor field effect transistor (MOSFE) chip. The DFN structure of the power MOSFE chip comprises an electric conduction base, a first electric conduction pad and a second electric conduction pad, wherein the electric conduction base is composed of a heat dissipation area and a base pin area, and the base pin area is composed of a plurality of drain pins which are arranged at intervals. One ends of the drain pins are in electric connection with the end face of the heat dissipation area, and the heat dissipation area is arranged directly below an MOSFE chip and in electric connection with the lower surface of the MOSFE chip through a soft solder layer. The first electric conduction pad and the second electric conduction pad are placed on the other side of the MOSFE chip and provided with solder zones and pin zones, and bend portions are arranged on connection portions of the solder zones and the pin zones. Quality percentage content of the soft solder layer is lead 92.5%, tin 5% and silver 2.5%. The DFN structure of the power MOSFE chip is beneficial to reducing the size of devices and the number of components inside a package body. In addition, the DFN structure of the power MOSFE chip can improve heat dissipation efficiency of a device MOSFE chip. Thermal resistance is reduced by 75% compared with the prior art.

Description

technical field [0001] The invention relates to the technical field of MOSFET chips, in particular to a DFN package structure of a power MOSFET chip. Background technique [0002] With the development of electronic products, consumer electronic products such as notebook computers, mobile phones, mini-CDs, palmtop computers, CPUs, and digital cameras are becoming more and more miniaturized. As products become smaller and thinner, how to dissipate the heat generated by millions of transistors in industrial ICs becomes a problem that has to be considered. In the prior art, although the calorific value can be reduced by improving the IC manufacturing process capability and reducing the voltage, the trend of increasing the calorific density cannot be avoided. If the heat dissipation problem is not solved, the reliability of the product will be affected due to overheating of the industrial device, which will seriously shorten the product life and even cause product damage. [00...

AI Technical Summary

Problems solved by technology

The exposed pins of the lead frame 930 are used to realize the electrical connection between the packaged chip 900 and the outside world, and the exposed function of the heat sink 920 is to dissipate the heat generated by the chip 900 to the environment through the exposed surface; Figure II It is another typical package structure, which also separates the pins from the heat sink, and the pins are exposed, and still has the technical problem of large volume and not conducive to heat dissipation

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