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Bus control device and bus control method

A technology of bus control and control unit, which is applied in the direction of bus network, data exchange through path configuration, transmission system, etc. It can solve the problems of time-consuming acquisition of fault information and failure to obtain fault information quickly, and achieve the effect of shortening the time

Inactive Publication Date: 2016-06-22
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, there is a problem that it takes time to obtain fault information via the serial bus
In addition, in Patent Document 1, failure data is added to response data, so failure information cannot be quickly obtained

Method used

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  • Bus control device and bus control method
  • Bus control device and bus control method
  • Bus control device and bus control method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings. figure 1 It is a block diagram showing the configuration of the bus control device according to the first embodiment of the present invention.

[0019] exist figure 1 Among them, the card 10 (main control circuit) is a circuit portion that mounts electronic circuits on the main control side including a host CPU (Central Processing Unit) (control unit) 101 .

[0020] The card 20 (controlled circuit) is a circuit part that mounts electronic circuits on the controlled side including the controlled devices 202-1 to 202-n (controlled targets). The control target devices 202 - 1 to 202 - n are devices such as EEPROM (Electrically Erasable and Programmable Read Only Memory; Electrically Erasable and Programmable Read Only Memory) or framers.

[0021] The card 10 and the card 20 are connected via a backplane (not shown), and exchange messages with each other via the serial bus ...

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PUM

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Abstract

In the bus control device configured to connect the circuit part on the master side and the circuit part on the slave side via the serial bus, it is possible to promptly notify the control unit on the master side of failure information of the device to be controlled. The master circuit equipped with the control unit generates an access message for accessing a control object mounted on the controlled circuit, and transmits the access message to the controlled circuit connected to the master circuit via a bus. The controlled circuit collects the information of the control object, generates a response message to the access message and an information message based on the information of the control object, and sends the response message and the information message to the master control circuit. In the case that the generation of the response message conflicts with the generation of the information message, the controlled circuit generates the information message preferentially.

Description

technical field [0001] The present invention relates to a bus control device and a bus control method configured as follows: a circuit part on the master side on which a host CPU (Central Processing Unit; central processing unit) is mounted, and a circuit part on the controlled side on which a device to be controlled is mounted BackWiring Board (BackWiringBoard) to connect, and communicate with each other via the serial bus. Background technique [0002] An information processing device such as a network device is configured by connecting the circuit part on the master side on which the host CPU is mounted, and the circuit part on the slave side on which the device to be controlled is mounted via the back wiring board, and physically connects them via transmission and reception. communicate with each other on separate serial buses. In such a configuration, messages are transmitted and received via the serial bus between the circuit unit on which the host CPU is mounted and ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L29/14G06F13/38H04L12/40H04L69/40
CPCH04L12/4015H04L41/06H04L69/40G06F13/4282G06F11/0745G06F11/0781G06F11/0784G06F13/22G06F11/0772G06F13/20
Inventor 田崎雄一
Owner NEC CORP