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Die executing test mode operation and method for performing test mode operation

一种测试模式、管芯的技术，应用在静态存储器、数字存储器信息、仪器等方向，能够解决浪费表面面积等问题

Active Publication Date: 2013-01-23
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In some cases, some signals are routed to traverse more than half the distance of the die 100, which is quite a waste of surface area that could be used for other circuits. In addition, these signals are only needed at startup.

Method used

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  • Die executing test mode operation and method for performing test mode operation
  • Die executing test mode operation and method for performing test mode operation

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0023] The present invention proposes a muxing mechanism, which switches the latching and decoding of the test mode signal at the address code group instead of at the electric fuse block. The present invention also provides a single bus to carry the test mode signal instead of multiple signal lines as in the prior art. This greatly reduces the amount of surface area required for signal routing and allows the size of the die to be reduced.

[0024] Please refer to FIG. 2 , which is a schematic diagram of an embodiment of a die 200 of the present invention. As shown in FIG. 2 , the die 200 includes an e-fuse block 210 having a plurality of e-fuses and a plurality of address code groups 230 , 240 , 250 , 260 . However, unlike the known test mode block 120, each address code group has a corresponding latch 232, 242, 252, 262, a first decoder 238, 248, 258, 268 and a second Decoders 236, 246, 256, 266 are placed regionally (that is, at the address code group) instead of being loc...

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PUM

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Abstract

The invention discloses a die which includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch.

Description

technical field [0001] The present invention relates to the initialization of test mode functions, and more particularly to a test mode multiplexing mechanism which can be used to reduce channel routing. Background technique [0002] A major consideration in modern semiconductor devices is reducing die size to enable smaller devices. Semiconductor memory usually includes a test mode circuit. In this technical field, when the memory is initialized, it will enter the test mode, and the test mode involves transmitting test mode signals from various electric fuses (efuses) to the address code group ( address block) to verify that all circuits are functioning properly. After all blocks have been checked, the test mode signal and e-fuse are not used anymore. [0003] Please refer to FIG. 1 , which shows a circuit layout design of a conventional die 100 . The die 100 includes an e-fuse block 110 having a plurality of e-fuses, which provides a plurality of test mode signals, and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/08
CPCG11C11/46G11C29/28G11C2029/0407
Inventor 赫尔曼·文柯
Owner NAN YA TECH