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Method using alignment mark in copper wiring metal injection molding (MIM) capacitance process

A technology for aligning marks and capacitors, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of no photolithography alignment, light-proof, etc., and achieve the effects of saving space, improving utilization, and reducing costs

Active Publication Date: 2013-02-20
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Failure to use an alignment mark layer can result in figure 2 As shown, since there is a layer of aluminum (AL) in the MIM capacitor layer, it is opaque and has no height difference, resulting in no alignment marks for photolithography alignment on the upper substrate layer and the lower substrate layer

Method used

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  • Method using alignment mark in copper wiring metal injection molding (MIM) capacitance process
  • Method using alignment mark in copper wiring metal injection molding (MIM) capacitance process
  • Method using alignment mark in copper wiring metal injection molding (MIM) capacitance process

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Embodiment Construction

[0022] The present invention will be further described below with reference to the drawings and specific embodiments, but it is not a limitation of the present invention.

[0023] The specific structure of an embodiment of the present invention is similar to the prior art, such as figure 1 As shown, it is divided into three process levels: an alignment mark layer, an upper substrate layer, and a lower substrate layer. The alignment mark layer also includes a metal dielectric layer (not shown) as the front process level; the alignment mark The layer is made on the chip dicing track for the lithographic alignment of the upper substrate layer and the lower substrate layer; the function of the upper substrate layer and the lower substrate layer is to make the entire MIM capacitor device, so the upper substrate layer and the lower substrate layer are common The MIM capacitor layer is formed; in the embodiment of the present invention, since there is no need to newly fabricate alignmen...

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Abstract

The invention discloses a method using an alignment mark in a copper wiring MIM capacitance process and belongs to the technical field of integrated circuit manufacture. The method comprises that an alignment mark of a former process layer is opened through photoresist, and other areas are blocked by the photoresist; etching process is conducted and copper is reserved; and an MIM capacitance layer is deposited, and the reserved copper serves as a photoetching alignment mark. The method has the advantages that the utilization rate of the chip space is improved, and chip resources are saved; a low-grade photomask is adopted, and the cost of the photomask is reduced; and the process in which silicon nitride is added is omitted, and the process cost is reduced.

Description

technical field [0001] The invention relates to integrated circuit manufacturing technology, in particular to a method for adopting an alignment mark in a copper MIM capacitance process. Background technique [0002] With the continuous miniaturization of integrated circuit technology, the current mainstream integrated circuit manufacturing has entered the stage of 65nm or even smaller. As line widths shrink and costs increase, real estate on chips is at a premium. How to reduce the chip space occupied by the chip dicing lines to increase the placement space and reduce the cost of semiconductor devices has become one of the main research topics in the industry. [0003] At present, there are three process levels in the copper process MIM (Metal Injection Molding, Metal Injection Molding) capacitor process in the industry: alignment mark layer (alignment mark layer); upper substrate layer and lower substrate layer. like figure 1 As shown in FIG. 1 , the alignment mark laye...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L23/544
Inventor 郑海昌朱骏张旭昇
Owner SHANGHAI HUALI MICROELECTRONICS CORP