Power hardware-in-the-loop (PHIL) interface system suitable for active tested system
A technology of the system under test and interface system, which is applied in the direction of electrical components, circuit devices, AC and DC network circuit layout, etc., can solve the problems that the interface cannot flexibly adjust the simulation effect of interface parameters, and it is difficult to adapt to the research and test requirements of active HUT. , to achieve the effect of improving the simulation effect, taking into account the accuracy, and improving the simulation accuracy
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[0044]A PHIL interface system suitable for the active system under test, used for the connection between the virtual electric system (VES) and the active system under test (HUT), using the ITM interface to realize the forward driving loop, and dragging through the four-quadrant power amplifier The device under test is used to collect the feedback state by voltage and current transformers, and the feedback channel is realized through the impedance-matched SDIM interface to form a system observer to observe the response of the device under test in the power system. This interface system gives full play to the respective characteristics of ITM interface and SDIM interface, and realizes impedance matching through impedance measurement algorithm, which greatly improves the simulation accuracy on the digital simulation side and the actual device side.
[0045] Such as figure 2 As shown, the PHIL interface system applicable to the active system under test in this embodiment includes...
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