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Memory management device, image processing device and integrated circuit

A memory management and memory technology, which is applied in the direction of memory systems, static memory, digital memory information, etc., can solve the problem of not being able to suppress the power consumption of unused memory banks, and achieve the effect of suppressing power consumption

Active Publication Date: 2015-11-25
PANASONIC SEMICON SOLUTIONS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] That is, there is a problem in the prior art A and the prior art B that the function of the unused bank cannot be suppressed according to the change of the allocation state of the memory corresponding to the access based on bank interleaving. consumption

Method used

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  • Memory management device, image processing device and integrated circuit
  • Memory management device, image processing device and integrated circuit
  • Memory management device, image processing device and integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0051] figure 1 It is a block diagram showing the structure of the data storage device 1000 of the first embodiment.

[0052] The data storage device 1000 includes a memory management unit (MMU (Memory Management Unit)) 100 , a DRAM 200 , and a DRAM control circuit 210 .

[0053] The memory management device 100 manages the state of the DRAM 200 which is a memory in accordance with a segment method which is a memory management method. The memory management device 100 performs a process of converting a logical address into a physical address, the details of which will be described later.

[0054] DRAM 200 has an autorefresh function and a selfrefresh function in order to save data stored in DRAM 200 . The automatic refresh is performed in accordance with instructions from an unshown external circuit. Automatic refresh is a well-known process, and thus will not be described in detail.

[0055] In particular, the DRAM 200 has a function of performing a partial self-refresh (p...

no. 2 Embodiment approach

[0217] In this embodiment, a configuration for causing the capacity setting unit 124 to execute the process of setting the guaranteed capacity CP based on two elements will be described. These two elements refer to the aforementioned total secured area capacity and the number of valid segments. The number of valid segments refers to the number of segments SG for which the validity determination information FG indicates "valid".

[0218] Figure 9 It is a block diagram showing the configuration of a data storage device 1000A according to the second embodiment.

[0219] refer to Figure 9 ,and figure 1 Compared to the data storage device 1000 shown, the data storage device 1000A differs in that a memory management device 100A is included instead of the memory management device 100 . The other configurations of the data storage device 1000A are the same as those of the data storage device 1000 , and therefore detailed descriptions will not be repeated.

[0220] and figure 1...

no. 3 Embodiment approach

[0264] In this embodiment, an image processing device including the data storage device 1000 or the data storage device 1000A will be described. As an example, an image processing device including the data storage device 1000 will be described in this embodiment.

[0265] Figure 12 It is a block diagram showing the configuration of the image processing device 2000 of the third embodiment. As an example, the image processing device 2000 is an imaging device. The imaging device is, for example, a network camera, a vehicle camera, a digital video camera, or a digital still camera.

[0266] refer to Figure 12 The image processing device 2000 includes a data storage device 1000 , a CPU 301 , a recording medium interface 310 , an encoding unit 321 , a decoding unit 322 , an image size changing unit 330 , and a display unit 340 .

[0267] Each part included in the data storage device 1000 has already been described in the first embodiment, and thus detailed description will not...

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Abstract

A memory management unit manages a state of a memory which is to be accessed by bank interleaving. The memory includes p banks (where p is an integer of 2 or greater). The memory management unit includes a control unit that dynamically determines a bank to be accessed from among the p banks. When predetermined conditions for a reserving state of the memory are satisfied and there is any unused bank in the p banks, the control unit performs power consumption reduction to control the memory to cause power consumption of the unused bank(s) to be less than power consumption of other banks in the p banks except the unused bank(s).

Description

technical field [0001] The present invention relates to a memory management device, an image processing device and an integrated circuit for managing a memory corresponding to bank-interleave-based access. Background technique [0002] In recent years, with the complexity and speed of system LSI (LargeScale Integration: Large Scale Integration), the operating frequency and power consumption of DRAM (Dynamic Random Access Memory: Dynamic Random Access Memory) have increased. Therefore, in the power consumption of the system, the proportion of the power consumption of the DRAM increases, and the energy saving of the DRAM becomes an issue that cannot be ignored. [0003] Therefore, in order to save energy in DRAM, Patent Document 1 discloses such a technology (hereinafter referred to as prior art A) that changes the address mapping from logical addresses to physical addresses according to the operation mode, and sets no memory The accessed physical storage area, and stop the p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06G06F12/00
CPCG11C11/40618G06F1/3225G06F1/3275Y02B60/1225Y02B60/1228Y02D10/00
Inventor 室山隆时枝美穗高田伸一山田光治
Owner PANASONIC SEMICON SOLUTIONS CO LTD