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Preparation method of metal nitride barrier layer

A technology of nitride and barrier layer, which is applied in the field of preparation of metal nitride barrier layer, can solve the problems of poor barrier performance, carrier trap effect, and influence on the conductive stability of metal wiring, and achieve the effect of improving compactness

Inactive Publication Date: 2013-04-03
BEIJING TAILONG ELECTRONICS TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1) Cu diffuses quickly in Si and its oxides and most dielectric layers, and once Cu enters the device, it will form deep-level impurities, which have a strong trap effect on the carriers in the device, making the device performance Degradation or even failure
[0006] 2) Cu is very easy to combine with Si and SiO below 200 ℃ 2 React to form copper-silicon compound causing component failure
[0007] 3) Cu has poor adhesion to dielectric materials, resulting in insufficient mechanical strength of thin films in integrated circuits
[0008] 4) Unlike Al, Cu can form a dense oxide protective layer, so it is easy to be oxidized and corroded, thus affecting the conductive stability of metal wiring
[0011] The TaN barrier layer is usually prepared by physical vapor deposition (Physical Vapor Deposition, PVD). One problem with this method is that the film is not dense enough and there are holes, which will lead to poor barrier performance.

Method used

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Embodiment Construction

[0025] The technical solution of the present invention will be described in detail below in conjunction with the embodiments.

[0026] An embodiment of the present invention provides a method for preparing a metal nitride barrier layer, which specifically includes the following steps:

[0027] (1) The Ta layer was deposited on the silicon wafer by the DC magnetron sputtering method in the physical vapor deposition method, and the background vacuum degree before sputtering was 10 -3 -10 -6 Pa, argon gas is introduced during sputtering. At this time, the vacuum degree is 0.1-1Pa. Sputtering is carried out under this vacuum degree. The sputtering speed is 0.1-1 nm / s, and the thickness of the sputtered Ta layer is 2-50nm.

[0028] (2) Simultaneously with DC magnetron sputtering, the ion source generates N ion beams, injects nitrogen ions into the metal Ta layer for nitriding, and the background pressure range of the ion source chamber is 10 -7 Pa~1000Pa, preferably 10 -5 Pa~10...

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Abstract

The invention discloses a preparation method of a metal nitride barrier layer, and belongs to the technical field of semiconductor device manufacturing. The metal nitride barrier layer is prepared by adopting a physical vapor deposition method; when a metal layer is deposited, an ion source on a physical vapor deposition device generates a nitrogen ion beam, and nitrogen ion is poured into a metal layer. According to the invention, a physical vapor deposition preparation method with the assistance of plasma is adopted, the compactness of the barrier layer is improved; meanwhile the fact that the barrier layer has an amorphous structure is ensured; and amorphousness has no channel for rapid diffusion, like the crystal boundary, and is an ideal barrier layer structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a method for preparing a metal nitride barrier layer. Background technique [0002] In the field of semiconductor technology, the earliest interconnection metal is Al. However, with the continuous improvement of the integration of devices, especially the development of VLSI, the feature size of devices is continuously shrinking, and the cross-sectional area and line of interconnection on the chip The pitch continues to decrease, which leads to the continuous increase of the interconnect resistance R and the parasitic capacitance C, which greatly increases the delay time constant RC of the interconnect. Since the delay time constant RC is taking an increasing proportion in the delay of the integrated circuit system, it becomes the main factor limiting the interconnection speed. [0003] In order to ensure the high speed, high integration, high stabilit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
Inventor 王文东夏洋李超波李勇滔刘训春
Owner BEIJING TAILONG ELECTRONICS TECH