Unlock instant, AI-driven research and patent intelligence for your innovation.

Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making

A semiconductor and gate region technology, applied in the field of self-aligned semiconductor devices and manufacturing with reduced gate-source leakage under reverse bias, can solve the problems of increasing the complexity and cost of the manufacturing process

Inactive Publication Date: 2013-04-10
PI
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for SiC, ion implantation requires multiple implants of different energies
Thus, processes involving wafer rotation and angled implants can add significantly to the complexity and cost of the manufacturing process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making
  • Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making
  • Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] The power junction field effect transistor JFET should remain in the off state even with a very large bias applied to the drain terminal (eg 600V-10kV). Therefore, a power JFET device should have minimal "drain-induced barrier lowering" (commonly referred to as "DIBL"). In the DIBL phenomenon, the applied drain voltage lowers the energy barrier between the source and drain, allowing unwanted leakage current to flow through the device.

[0036] To minimize the DIBL effect so that the power transistor blocks large voltages (e.g. 600 V-10 kV), an off-state energy barrier should occur near the source electrode and there should be a barrier separating the drain from the source "Long channel". In effect, the energy barrier (which is modulated by the bias voltage applied to the p+ gate) should be as far away from the drain as possible to minimize DIBL. This is accomplished by positioning the narrowest part of the channel near the source, as is the case for JFETs with sloped ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+ / n / n+ or a p+ / p / n+ gate-source junction is described. The device gate can be self- aligned to within 0.5 um to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of prior Provisional US Patent Application Serial No. 61 / 347928, filed May 25, 2010, which is hereby incorporated by reference in its entirety. [0003] The section headings used herein are for organizational purposes only and should not be construed as limiting in any way the subject of the present invention. [0004] background technical field [0005] The present application relates to semiconductor devices and methods of fabricating devices, and in particular, to wide band-gap semiconductor devices, such as silicon carbide SiC vertical channel junction field effects with reduced gate-source leakage under reverse bias transistor. Background technique [0006] To date, vertical-channel SiC junction field-effect transistors have been proposed as devices with vertical or nearly vertical sidewalls [1, 2]. However, in devices with vertical or near-vertical sidewalls, it is difficult...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/0657H01L29/1066H01L29/1608H01L29/66068H01L29/66909H01L29/7722H01L29/8083
Inventor 安德鲁·里特诺尔大卫·C·谢里登
Owner PI