Signal sampling caching device used for field programmable gata array (FPGA) chip debugging

Abstract

The invention discloses a signal sampling caching device used for field programmable gata array (FPGA) chip debugging. The signal sampling caching device used for FPGA chip debugging comprises a caching controller (1), a test plug seat (2), a storage module (3), a communication interface (4) and a cascading plug seat module used for achieving the cascade connection among a plurality of signal sampling caching devices. The caching controller (1) is respectively connected with the test plug seat (2), the storage module (3), and the communication interface (4). The cascading plug seat module comprises a first cascading plug seat (5) and a second cascading plug seat (6), wherein the first cascading plug seat (5) and the second cascading plug seat (6) are respectively used for being connected with a signal sampling caching device in an upper grade or a signal sampling caching device in a lower grade in a cascading working state. The first cascading plug seat (5) and the second cascading plug seat (6) are respectively connected with the caching controller (1). The signal sampling caching device used for FPGA chip debugging has the advantages of having no use for random access memory (RAM) resource in an FPGA chip and being high in usage ratio of storage space, large in signal sampling time span, strong in multiple signal sampling ability and flexible in usage method.

Description

technical field [0001] The invention relates to the field of logic debug (debugging) in FPGA applications, in particular to a signal sampling buffer device for FPGA chip debugging. Background technique [0002] As a reprogrammable logic array chip, FPGA is widely used in the design of prototype verification systems and batch products. User logic generates a corresponding bit stream through logic synthesis, resource mapping, and layout and routing processes through the design tools provided by the FPGA manufacturer. After the bit stream is imported into the FPGA chip, specific applications can be executed. Due to the advantages of flexible application and reprogrammable FPGA chips, the use of FPGA chips for prototype system design has become an important means of logic verification before most ASICs are put into production. [0003] FPGA chips, like ASIC chips, face the problems of difficulty in observing internal signals, which is not conducive to logic debugging. For this...

AI Technical Summary

Problems solved by technology

If the user's logic resources occupy a large amount and the timing requirements are strict, especially when the on-chip RAM usage is large, debugging tools such as ChipScope usually cannot be used normally. On the one hand, the resources are limited and the debugging logic that the user expects cannot be completed. Insertion; on the other hand, the increased debugging logic affects the layout and routing of user logic, and even fails due to timing failure

[0004] Although several major FPGA manufacturers have provided more convenient and functional internal signal observation tools, they are all limited by the very limited on-chip RAM resources inside the chip, and cannot meet the long-term requirements for internal signal observation. logic debug

If you use a high-end logic analyzer for signal sampling, on the one hand, it is expensive, and on the other hand, the storage depth is still very limited

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