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Packet clock recovery method and device

A technology of clock recovery and clock generator, which is applied in the field of communication and can solve the problems of large clock recovery errors

Active Publication Date: 2016-12-14
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Aiming at the problem in the related art that the selection of time windows for short messages leads to large clock recovery errors, the present invention provides a packet clock recovery method and device to at least solve the above problems

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  • Packet clock recovery method and device

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Embodiment Construction

[0030] Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0031] It is mentioned in the related technology that in each microscopic phase detection cycle based on PDV data, although a shorter phase detection cycle has the advantage of being able to reflect clock changes faster, the data represented by the time window selected by the short message may It reflects the correct original clock information, and may also reflect error information caused by delay jumps and other factors.

[0032] In order to solve the above technical problems, the embodiment of the present invention provides a packet clock recovery method, the processing flow of which is as follows figure 1 As shown, including step S102 to step S106:

[0033] Step S102, obtaining the first loop c...

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Abstract

The invention discloses a grouping clock recovery method and device, the method comprising: obtaining the first loop control value generated by the current short message selection time window; using a sliding window to check the accuracy of the first loop control value Judging, wherein, starting from the current short message selection time window, establishing the sliding window with M consecutive short message selection time windows forward; generating a clock generator control value according to the decision result, controlling clock generation, and recovering packet clock. The invention can solve the problem in the related art that the short message selection time window causes relatively large clock recovery errors.

Description

technical field [0001] The present invention relates to the field of communications, in particular to a packet clock recovery method and device. Background technique [0002] When a packet message traverses different networks such as routers and switches, it passes through each node, and delays will be introduced in various links such as message scheduling and forwarding. For packet packets, the specific delay is affected by various factors such as the forwarding design of specific devices, the size of background traffic, the length of background packets, and QOS (Quality of Service, Quality of Service) scheduling policies. [0003] At present, clock recovery is performed on the packets after the packet packets traverse the packet network to ensure loop accuracy. The main clock recovery methods used are ACR (Large-scale Access Convergence Router, large-scale access router) adaptive technology used in 1588 and PWE3 (Pseudo-Wire Emulation Edge to Edge, edge-to-edge pseudowire...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04L12/70
Inventor 何力李争齐
Owner ZTE CORP