Manufacturing method of gate, manufacturing method of transistor

Abstract

The invention provides a production method of a grid. The production method of the grid comprises forming an inverted cone shape grid on a substrate of a semiconductor and performing annealing process on the inverted cone shape grid to improve the shape of the grid. The inverted cone shape grid can be made of amorphous silicon, monocrystalline silicon, polycrystalline silicon, amorphous germanium, monocrystalline germanium, silicon germanium metal or metal alloy materials. A silica layer on the semiconductor substrate is formed before the inverted cone shape grid is formed and the inverted cone shape grid is formed on the upper portion of the silica layer. The invention also provides a production method of a transistor. The production method of the grid has the advantage of obtaining a grid structure which is flat in surfaces, free of footing or small in footing and free of twisting on a lateral wall by performing the annealing process on the inverted cone shape grid.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a method for manufacturing a gate and a transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, integrated circuit chips are developing towards higher component density and high integration. In the development process of semiconductor devices, the quality of the gate directly affects the performance of the transistor and the quality of the semiconductor device. [0003] Taking an NMOS transistor as an example, the existing specific process for forming a gate is as follows: Refer to figure 1 As shown, a semiconductor substrate 100 is provided, and ions are doped in the semiconductor substrate 100 to form a P-type doped well (not shown); a gate dielectric layer is formed on the semic...

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Problems solved by technology

However, in actual production, the gate structure prepared by the above method has obvious defects

For example, in the process of etching the polysilicon layer 104 using a mask, a base angle 1041 is usually formed at the junction between the bottom surface of the formed gate 104a and the gate dielectric layer 102a, as Figure 5 Shown in (a), and the surface of gate 104a is also relatively rough, and these all can influence the performance of gate

In order to improve the roughness of the surface of the gate 104a, the surface of the gate 104a is usually annealed, such as figure 2 shown in ; however, although the annealing treatment here can improve the surface roughness, it will distort the sidewall of the gate 104a, as Figure 5 As shown in (b), this is also undesirable

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