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Semiconductor encapsulation element and manufacture method of semiconductor encapsulation element

A semiconductor and packaging technology, which is applied in the field of semiconductor packaging and its manufacturing, can solve the problems of increasing the cost, size and area of ​​the semiconductor packaging.

Active Publication Date: 2013-06-12
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the independently manufactured passive components lead to increased cost and size of the semiconductor package

Method used

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  • Semiconductor encapsulation element and manufacture method of semiconductor encapsulation element
  • Semiconductor encapsulation element and manufacture method of semiconductor encapsulation element
  • Semiconductor encapsulation element and manufacture method of semiconductor encapsulation element

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Embodiment Construction

[0055] Please refer to Figure 1A , which shows a cross-sectional view of a semiconductor package according to an embodiment of the present invention. The semiconductor package 100 is, for example, a quad flat no leads package (Quad Flat No leads, QFN), which includes a lead frame 110, at least one semiconductor chip 120, at least one bonding wire 130, a package body 140, at least one first capacitor dielectric layer 150 and at least one first capacitive conductive layer 160 .

[0056] The lead frame 110 includes a chip holder 111 and external leads 112 which are isolated from each other. The chip holder 111 is exposed from the lower surface 140 b of the package body 140 to conduct or convect the heat of the semiconductor chip 120 to the outside. The outer leads 112 have an outer side 112s exposed from an outer side 140s of the package body 140 . In addition, the external leads 112 have a lower surface 112b, and the lower surface 112b is exposed from the lower surface 140b o...

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PUM

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Abstract

The invention relates to a semiconductor encapsulation element, which comprises a conducting wire frame, a semiconductor chip, a first capacitance conducting layer, a first capacitance dielectric layer, a welding wire and an encapsulation body, wherein the conducting wire frame comprises a chip seat and an outer lead pin which are mutually isolated, the semiconductor chip is arranged on the chip seat, the first capacitance dielectric layer is formed on the chip seat and is in parallel configuration with the semiconductor chip, the first capacitance conducting layer is formed on the first capacitance dielectric layer, the welding wire is electrically connected with the semiconductor chip and the first capacitance conducting layer, the encapsulation body covers the semiconductor chip, the first capacitance conducting layer, the first capacitance dielectric layer and the welding wire, and the outer side surface of the outer lead pin is exposed out of the encapsulation body.

Description

technical field [0001] The present invention relates to a semiconductor package and its manufacturing method, and in particular to a semiconductor package with passive components and its manufacturing method. Background technique [0002] Conventional semiconductor packages include several I / O contacts for electrical connection to an external circuit board. However, static electricity and interference contained in the power supply can also enter the semiconductor package through the output / input contact, and damage the electronic components inside the semiconductor package. The traditional solution is to bond independently manufactured passive components to the substrate by surface mount technology. However, the independently manufactured passive components lead to increased cost and size of the semiconductor package. Contents of the invention [0003] The present invention relates to a semiconductor package and its manufacturing method. In one embodiment, passive compon...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/64H01L21/60
CPCH01L23/495H01L23/642H01L2224/48091H01L2224/48195H01L2924/00014
Inventor 颜瀚琦沈伟特林政男
Owner ADVANCED SEMICON ENG INC