High dielectric metal gate MOS and manufacturing method thereof
A metal gate, high dielectric technology, applied in semiconductor/solid state device manufacturing, circuits, electrical components, etc., can solve the problems of high cost, poor process controllability, complicated steps, etc., to reduce parasitic resistance, reduce series resistance, Avoid the effect of lowering the breakdown voltage of the device
Active Publication Date: 2015-11-25
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0007] The invention provides a high-dielectric metal gate MOS and its manufacturing method, which solves the problems of poor process controllability, cumbersome steps and high cost when gaps are formed in the existing process
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[0034] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.
[0035] The invention provides a method for manufacturing a high dielectric metal gate MOS, such as figure 2 shown, including:
[0036] Provide a silicon substrate, and sequentially form a gate oxide layer, a dummy polysilicon layer and a hard mask layer on the silicon substrate;
[0037] patterning the hard mask, and sequentially etching the dummy polysilicon layer and the gate oxide layer using the patterned hard mask as a barrier to form a gate structure;
[0038] Using the gate structure as a mask, performing ion implantation on the silicon substrate to form a deep junction lightly doped drain region;
[0039] A first sidewall is formed on the side of the gate structure, and ion implantation is performed on th...
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The invention provides a high-dielectric metal gate metal oxide semiconductor (MOS) and a manufacturing method of the high-dielectric metal gate MOS. Low-resistance metal silicide can be controllably formed in a light dope drain region through forming deeper junction light dope drain regions, parasitic resistance of the light dope drain region is reduced, so that series resistance of the whole is reduced, and a shallow groove with the depth larger than the junction depth of the light dope drain region is formed on a substrate between the deeper junction light dope drain regions, so that a part of a high-dielectric metal gate structure is embedded between the deeper junction light dope drain regions, channel regions of devices are located under the deeper junction light dope drain regions, and the problem that breakdown voltage of the devices becomes low caused by the deeper junction light dope drain regions is avoided.
Description
technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a high dielectric metal gate (highk-metalgate, HKMG) MOS (metal oxide semiconductor) and a manufacturing method thereof. Background technique [0002] With the development of semiconductor devices and integrated circuits, the size of semiconductor devices is getting smaller and smaller. For semiconductor devices, when the feature size of the device becomes smaller, a strong electric field can be generated even at a low voltage. This tends to cause hot carriers to appear. Therefore, in small-scale devices and large-scale integrated circuits, hot carriers are prone to appear, that is, the hot-carrier effect, and the hot-carrier effect is often an important cause of failure of devices and integrated circuits, so it is necessary to special Be careful and prevent. [0003] In order to solve the hot carrier effect, a lightly doped drain (lightly doped drain, LDD) te...
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IPC IPC(8): H01L21/336H01L21/28H01L29/78
Inventor 刘金华
Owner SEMICON MFG INT (SHANGHAI) CORP