Low temperature high coverage side wall manufacturing method

Abstract

The invention discloses a thin film manufacture method which includes: cleaning a cavity, stabilizing the cavity, and feeding wafer to the cavity; feeding reaction gas and dilution protective gas, and controlling the pressure of a reaction cavity to be smaller than or equal to 0.2T; stimulating radio frequency to generate plasma, and enabling the reaction gas adsorbed on the wafer to react to form thin film materials, wherein the temperature of the reaction cavity is controlled to be 200-400 DEG C; and closing the radio frequency after the required thickness growing of thin films is finished, stopping from feeding the reaction gas, and taking the wafer out. According to the thin film manufacture method, by controlling a plasma enhanced chemical vapor deposition (PECVD) method and controlling the technical parameters including temperature of devices, radio frequency (RF) and pressure, good syntype thin films with high stair coverage rate and high bottom filling rate can be obtained, and the insulating and isolating performance of devices are improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a side wall with low temperature and high coverage. Background technique [0002] In the manufacture of integrated circuits, it is often necessary to form dense sidewall protection on both sides of the gate, which is very important. On the one hand, the sidewall is to protect the gate, and on the other hand, it prevents a large dose of source and drain implantation from being too close to the conductive channel so that conduction between the source and the drain may occur. Therefore, the good shape and quality of the sidewall often play a crucial role in the reliability of the device. [0003] Especially with the development of semiconductor manufacturing technology to higher technology nodes, the size of the gate is getting smaller and smaller, the required thermal budget is getting lower and lower, and the conductive channel in the...

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Problems solved by technology

but Figure 1B , 1C Corresponding to different deposition parameters, the formed films with different conformalities have different shapes of sidewalls during the etching process. For MOSFETs with insufficient conformality, the sidewalls may be broken, interrupted or deformed, or formed The width of the sidewall is not enough, which affects the insulation and isolation effect of the device and reduces the performance of the device

[0006] Therefore, how to reasonably control the deposition reaction parameters at low temperature to improve the conformality of sidewall films is a huge challenge for the development of current MOSFET technology, especially sub-20nm MOSFET technology.

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