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Completely integrated circuit for generating ramp signal

A circuit and signal technology, applied in the field of integrated circuits that generate ramp signals, can solve problems such as the single ramp slope of the ramp generator circuit

Active Publication Date: 2013-07-03
STMICROELECTRONICS (SHENZHEN) R&D CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Prior art ramp generator circuits are also typically limited to a single (fixed) ramp slope

Method used

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  • Completely integrated circuit for generating ramp signal
  • Completely integrated circuit for generating ramp signal
  • Completely integrated circuit for generating ramp signal

Examples

Experimental program
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Embodiment Construction

[0016] now refer to figure 1 , which is a circuit diagram of the ramp generator circuit 10 . Circuit 10 includes an input node 12 that receives a clock signal Fsw. Programmable divide circuit 14 divides clock signal Fsw to generate divided clock signal CLK on line 16 . Programmable division circuit 14 implements clock division by n. The control circuit 18 supplies the programmable division circuit 14 with a divisor n value, which can be selected by the control circuit. As will be discussed in more detail below, selection of the value of divisor n sets the slope of the generated ramp signal output by circuit 10 .

[0017] The circuit 10 further includes a flip-flop circuit 20 . A preferred implementation uses a D-type flip-flop for flip-flop circuit 20 . The data "D" input of the D-type flip-flop circuit 20 is connected to a node associated with the first reference voltage (in this case the high reference voltage Vdd). The clear “CLR” input of D-type flip-flop circuit 20 ...

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PUM

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Abstract

The invention relates to a completely integrated circuit for generating a ramp signal. The completely integrated circuit comprises a first current generator, wherein the first current generator provides current to a first capacitor through a first transistor, and the grid control is carried out on the first transistor by a complementary signal of a periodic signal. Ramp voltage stored on the first capacitor is buffered to an output node to be taken as a ramp output signal. An output node is coupled to the first current generator by a second transistor, and the grid control is carried out on the second transistor by the periodic signal. The periodic signal is generated at the output place of a trigger for receiving an input clock signal and a reset signal. The reset signal is generated by a comparator circuit operable to compare voltage on a second capacitor with the reference quantity. A second capacitor is charged by a second current source, and is discharged by a third transistor, wherein the grid control is carried out on the third transistor by the periodic signal.

Description

technical field [0001] The present invention relates to integrated circuits, and more particularly, to integrated circuits configured to generate ramp signals. Background technique [0002] Circuits for generating ramp signals, such as used in soft-start circuits, are well known in the art. These circuits may include capacitors, but in many cases capacitors are of a size that cannot be easily integrated. There is a need in the art for ramp generator circuits that can be fully integrated. [0003] Prior art ramp generator circuits are also generally limited to a single (fixed) ramp slope. There is a need in the art for ramp generator circuits that support adjustable ramp slopes. Contents of the invention [0004] In one embodiment, a circuit includes: a first current generator coupled between a first reference voltage node and a first intermediate node; a first transistor source-drain coupled between the first intermediate node and a second between the intermediate node...

Claims

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Application Information

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IPC IPC(8): H03K4/02
CPCH03K4/502
Inventor 黄涛涛王蒙
Owner STMICROELECTRONICS (SHENZHEN) R&D CO LTD
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