Super potential barrier rectification device with inclined grooves, and manufacturing method thereof

Abstract

The invention discloses a super potential barrier rectification device with inclined grooves, which can not increase light times while overcoming the parasitic JEFT effect. The super potential barrier rectification device comprises a semi-conductor substrate, wherein the upper part of the semi-conductor substrate is a first conduction type drift region, the surface of the drift region is a first main surface, the lower part of the semi-conductor substrate is a first conduction type substratum, and the surface of the substratum is a second main surface; one or more inclined grooves is / are formed in the first main surface; the inclined grooves covered with isolated gate oxidizing layers are filled with conductive polycrystalline silicon, second conduction type injection regions are arranged at the peripheries of the inclined grooves or at the positions where every two adjacent inclined grooves are close to the first main surface; second conduction type injection regions are arranged at the adjoining parts of the upper edges of the inclined grooves and the first main surface; a first metal layer is deposited on the conductive polycrystalline silicon and the first main surface; a second metal layer is deposited on the second main surface. The invention further discloses a manufacturing method of the super potential barrier rectification device with the inclined grooves.

Description

technical field [0001] The invention relates to a semiconductor discrete device and a manufacturing method thereof, in particular to a super-barrier rectifying device and a manufacturing method thereof. Background technique [0002] The existing power semiconductor rectifier devices are divided into two types according to the barrier type, one is a Schottky barrier rectifier, and the other is an integrated MOS channel super-barrier rectifier device. Among them, the Schottky rectifier device is a rectifier device made by contacting a noble metal (such as gold, silver, platinum, titanium, nickel, molybdenum, etc.) with a semiconductor to form a Schottky barrier. Schottky barrier rectifiers have been gradually integrated into MOS channel super-barrier rectifiers due to their shortcomings such as high forward voltage drop, low reverse withstand voltage level, large reverse leakage, and heavy metal pollution caused by the process. replaced. [0003] The integrated MOS channel s...

AI Technical Summary

Problems solved by technology

There is a parasitic JFET resistance in the planar MOS structure, which prevents the further reduction of the forward voltage drop VF of the rectifier; and the channel region of the planar MOS structure is on the surface of the device, which wastes the area of ​​the wafer surface and is not conducive to the improvement of chip integration.

[0005] Chinese patent CN201010135350.0 discloses a structure and manufacturing method of an integrated MOS super-barrier rectifier device. The integrated MOS unit in the rectifier device adopts a trench structure (see the appendix for the specific structure. image 3 ), although the trench structure rectifier overcomes some shortcomings of the planar MOS structure of Chinese patents ZL01143693. Area illumination, groove illumination, and metal layer illumination) have become at least five times (protective ring illumination, active area illumination, groove illumination, deep hole illumination, and metal layer illumination each once). As we all know, with the semiconductor rectifier With the increasing maturity of component technology and increasingly fierce market competition, how to reduce the manufacturing cost under the premise of ensuring device performance has become a common concern of semiconductor technicians. In the semiconductor manufacturing process, the number of times of illumination determines the manufacturing cost. How to reduce the number of times of illumination as much as possible under the premise of ensuring the performance of the device; because the rectifier device disclosed in Chinese patent CN201010135350.0 not only increases the number of times of illumination during the manufacturing process, but also has more injection, thermal diffusion, and deep hole engraving. The multi-step process such as etching increases the manufacturing cost by about 25-30%. In addition, its P- and P+ wells determine the Ir and Vf characteristics of the device, especially the p+ well depth. If the P+ well depth exceeds the trench depth, then The trench cannot eliminate the JEFT effect, and the JEFT effect still exists between the P+ wells. If the P+ depth is shallower than the trench depth, there is a JEFT effect between the P+ and the trench. Only when the P+ depth is equivalent to the trench depth, the JEFT effect It will be reduced to a certain extent, which has caused problems such as small process windows and design windows and ineffective effects, and difficulty in mass production.

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