A Chip Packaging Structure with Power Noise Isolation

Abstract

The invention discloses a chip packaging structure with power supply noise isolation. The chip packaging structure with power supply noise isolation comprises a first packaging element. The first packaging element comprises a first substrate and a first semiconductor chip, wherein the first substrate is provided with a first surface and a second surface which are opposite to each other, and the first semiconductor chip is installed on the first surface of the first substrate. The first substrate is provided with a first integrated isolation function structure. The first integrated isolation function structure comprises a first electromagnetic band-gap structure, a first inductance device and a first energy storage device. The chip packaging structure with power supply noise isolation can effectively solve the problems of isolation with large bandwidth and high isolation of the power supply noise of chip packaging (comprising two-dimensional packaging and three-dimensional packaging).

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a chip packaging structure with power supply noise isolation. Background technique [0002] As the size of electronic devices decreases, high integration density can be achieved by stacking a plurality of chips in one semiconductor package or stacking a plurality of individual semiconductor packages. Recently, stacked semiconductor packages have been introduced for mobile electronic device applications and the like. One of the stacked semiconductor packages is a package-on-package (POP) in which a logic package device and a memory package device are stacked. Using the POP technology, different types of semiconductor chips can be included in one semiconductor package. [0003] As the pitch of each chip in the same package is reduced to tens of microns, mutual power noise interference increases; especially when RF chips, analog chips or micro-sensing chips are included in a...

AI Technical Summary

Problems solved by technology

The above electromagnetic bandgap (EBG) structure shows that when its operating frequency is in the range of 1-10GHz, the size of one cycle is about 30mm×30mm, which is larger than the entire package area, which is obviously not suitable for package substrates or plug-in boards.

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