A layered system and method for implementing cache coherency protocol
A high-speed cache and consistency technology, which is applied in memory systems, instruments, and electrical digital data processing, etc., can solve problems such as low maintenance efficiency, high bus bandwidth requirements, and small number of cores, achieving good real-time performance, improving maintenance efficiency, and The effect of reducing frequency of use and occupied time
Inactive Publication Date: 2017-04-05
XIDIAN UNIV
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[0010] The purpose of the present invention is to address the deficiencies of the above-mentioned existing protocols, combining the respective advantages and disadvantages of the shared bus architecture, the on-chip interconnection network architecture and its cache coherence protocol, to propose a multi-core processor cache coherence method to solve the problem of bus The number of cores supported by the monitoring protocol is small, the bandwidth requirements of the bus are high, and the maintenance efficiency is low
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[0045] The present invention will be further described below in conjunction with the accompanying drawings.
[0046] Such as Figure 1~4 As shown, the present invention is a layered system for implementing a cache coherency protocol. There are multiple cores in the system, and the multiple cores are divided into several groups, and each group serves as a node, which is the first node of the system. One layer; between the nodes is the second layer of the system; the node is provided with a node controller, one end of the node controller is connected to the home node controller, and the other end of the home node controller One end is respectively connected with the node directory storage and the second-level cache.
[0047] It should be noted that each core in the node is also connected to a cache controller;
[0048] A cache storage module, one end is connected to the core, and the other end is connected to the cache controller;
[0049] a cache directory storage connected ...
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The invention discloses a layering system for achieving the caching consistency protocol and a method of the layering system. According to the scheme, the bus monitoring protocol is adopted in the first layer of the layering system to enable the first layer of the layering system to adapt to a sharing bus framework of the first layer of the layering system, the caching consistency protocol based on a catalog is adopted in the second layer of the layering system to enable the second layer of the layering system to adapt to an internet framework on an NoC of the second layer of the layering system, the two frameworks transmit consistency maintenance signals sent by the two protocols through a node controller of each node, the two protocols can be mutually communicated, and then the mixed consistency protocol can maintain the caching consistency of the whole system. The method has the advantages of being high in performance, good in real-time performance, high in expandability and low in design complexity, solving the bus bandwidth problem of the sharing bus framework, solving the problem that the catalog in the consistency protocol based on the catalog is excessively large in occupied storage space, and enabling the consistency protocol to better adapt to lager-scale multi-core processors.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a multi-core processor cache hybrid consistency architecture with a layered architecture, which is used to solve the problem of data conflicts caused when multi-core processors access shared data. Background technique [0002] With the continuous development of integrated circuit technology, it is increasingly difficult for traditional single-core microprocessors to meet application requirements. Due to the advantages of multi-core processors in terms of power consumption and speed compared with single-core processors, they have been greatly improved in recent years. develop. [0003] A multi-core processor integrates multiple computing cores into one processor, uses parallel processing technology to distribute tasks to multiple computing cores, and makes full use of processor resources to improve processor performance. However, with the increase of the structural co...
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IPC IPC(8): G06F15/163G06F12/0811G06F13/16
Inventor 蔡觉平凌鹏齐艺兰张泽滕国文李琰余军毕文婷李赟伟
Owner XIDIAN UNIV