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Address change monitoring circuit, device and generating method thereof

A technology of change monitoring and address, applied in the direction of information storage, static memory, digital memory information, etc., to meet different needs and meet the effect of reading speed

Active Publication Date: 2016-04-20
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the prior art, it is difficult to generate address change monitoring circuits with various speeds (different valid times T) through automatic algorithms

Method used

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  • Address change monitoring circuit, device and generating method thereof
  • Address change monitoring circuit, device and generating method thereof
  • Address change monitoring circuit, device and generating method thereof

Examples

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Embodiment Construction

[0024] Embodiments of the present technology will be described in detail below with reference to the accompanying drawings. While described in conjunction with embodiments, it will be understood that it is not intended to limit the present technology to these embodiments. On the contrary, the technology is intended to cover various alternatives, modifications and equivalents as defined within the spirit and scope of the technology as defined by the appended claims.

[0025] In addition, in order to better understand the present technology, a large number of specific details are set forth in the following description, such as specific circuits, devices, connection relationships, and the like. However, it will be understood by those of ordinary skill in the art that the technology may be practiced without these specific details. In some other embodiments, well-known technologies are not described in detail in order to highlight the gist of the technology.

[0026] The specific...

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PUM

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Abstract

The invention discloses an address change monitoring circuit, device and method. The address change monitoring circuit comprises a zero clearing and delaying unit, an overturning unit and a judging unit, wherein the zero clearing and delaying unit is used for receiving an input signal at a second input end and receiving an inverted input signal at a first input end; the overturning unit is serially connected between a first output end and a second output end; the judging unit outputs a sequence signal based on a logic relationship between signals on the first output end and the second output end. According to the method provided by the embodiment, address change monitoring circuits of different speeds can be generated, and the requirement of storage circuits of different sizes is met.

Description

technical field [0001] The technology generally relates to address change monitoring used in storage integrated circuits, and specifically relates to an address change monitoring circuit, device and method for generating the circuit. Background technique [0002] Many integrated circuits need to use storage circuits, such as static random access memory or flash memory, to temporarily store intermediate data required for the operation of electronic systems, or to store certain recorded data for a long time. An address change monitoring circuit is often integrated in the storage circuit, which generates a timing control signal required for the storage circuit to perform a read operation when the storage address changes. [0003] Such as figure 1 As shown, the address change monitoring circuit according to the prior art includes a plurality of address transfer monitoring (ATD) units 101 and logic circuits 102 (such as figure 1 logic OR circuit shown). Multiple input terminal...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413
Inventor 陈巍巍陈岚
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI