Address transition signal detection circuit

Abstract

The invention provides an address converting signal detecting circuit. The address converting signal detecting circuit is characterized by comprising a delaying and amplifying circuit, wherein the delaying and amplifying circuit delays an input address signal for inverted output, and amplifies the input address signal for output. Through adoption of the delaying and amplifying circuit, the input address signal can be delayed for inverted output and the input address signal can be amplified for output, thus avoiding attenuation of the address signal and facilitating use of a follow-up circuit.

Description

technical field [0001] The invention relates to an asynchronous circuit system, in particular to an address signal transition detection circuit. Background technique [0002] In the operation of asynchronous circuit system especially SRAM memory, when there is a change on the address line, it means to start a new read or write cycle. Although SRAM has no external clock and does not require additional timing and control signals, its memory operations are initiated by events on the address bus or the R / W signal. But this means that all circuits (like decoders and sense amplifiers) are implemented completely statically, so a change on one of the input signals (data or address bus, R / W) will pass through subsequent circuit levels in a primary and secondary manner. Therefore, such an all-static method is not feasible for larger-capacity memories in terms of area or power consumption. Therefore, it is necessary to generate a similar clock signal to trigger some internal circuits...

AI Technical Summary

Problems solved by technology

[0005] like figure 1 It is an address transition detection circuit commonly used in the prior art. Although this traditional address transition detection circuit can meet the requirements to a certain extent, the address signal is weakened during the detection of the address transition, so that the To a large extent, the output address signal is weak, which also makes the address signal weaker, which is not conducive to the use of subsequent circuits. Even if the detected address transition signal is amplified, it will also affect subsequent circuits.

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