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Group iii-v compound semiconductor device with metal contacts and manufacturing method thereof

A III-V, -III-V technology, applied in the field of III-V compound semiconductor devices and their manufacture

Active Publication Date: 2016-02-24
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One challenge is to reduce the resistance in the source / drain (S / D) extension structure to maximize transistor performance in III-V semiconductor CMOS technology

Method used

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  • Group iii-v compound semiconductor device with metal contacts and manufacturing method thereof
  • Group iii-v compound semiconductor device with metal contacts and manufacturing method thereof
  • Group iii-v compound semiconductor device with metal contacts and manufacturing method thereof

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Embodiment Construction

[0049] The description of the exemplary embodiments should be read in conjunction with the accompanying drawings, which are considered a part of this entire written specification. In the specification, relative terms such as "lower", "upper", "horizontal", "vertical", "above", "below", "upward", "downward", "top" and "bottom" and Derivatives thereof (eg, "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to an orientation as subsequently described or as shown in the drawings in the discussion. These relative terms are for convenience of description and do not require that the device be constructed or operated in a particular orientation. Unless expressly stated otherwise, terms relating to joining, connecting, etc. (such as "connected" and "interconnected") refer to a relationship in which some structures are affixed or joined to other structures, directly or indirectly through intervening structures, and both. Both are movable or rigid joints or rel...

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Abstract

A semiconductor device includes a semiconductor substrate; a channel layer comprising at least a first III-V group semiconductor compound located above the semiconductor substrate; a gate stack structure located above a first portion of the channel layer; a second portion of the channel layer located a source region and a drain region comprising at least a second group III-V semiconductor compound over the two portions; and a first metal contact structure over the S / D region comprising a first metallized contact layer contacting the S / D region . The first metallization contact layer includes at least one metal-III-V semiconductor compound. The present invention provides a III-V compound semiconductor device with a metal contact and a method of manufacturing the same.

Description

technical field [0001] The present invention relates to a III-V compound semiconductor device and a manufacturing method thereof. Background technique [0002] As complementary metal-oxide-semiconductor (CMOS) devices shrink to smaller dimensions, new materials and concepts are being considered to meet advanced performance goals. [0003] CMOS technology includes N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS). For example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a transistor used to amplify or switch electronic signals. One aspect of high performance in NMOS and PMOS, as well as various other devices, is the device switching frequency. Contacts are made for the gate electrode and source and drain regions of the transistor. [0004] Group III-V compound semiconductors are potential channel materials for future CMOS devices due to their high mobility and low effective mass. One challenge is to reduce the resistan...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/092H01L29/45H01L29/78H01L21/8238H01L21/28
CPCH01L29/45H01L27/0605H01L21/28575H01L29/7839H01L29/205H01L23/485H01L23/53266H01L29/78681H01L2924/0002H01L2924/00H01L29/475H01L29/452H01L29/4933H01L29/7833H01L29/20H01L29/78
Inventor 查理德·肯尼斯·奥克斯兰德
Owner TAIWAN SEMICON MFG CO LTD