Unlock instant, AI-driven research and patent intelligence for your innovation.

Anti-single event transient pulse cmos circuit

A transient pulse and anti-single event technology, which is applied in the direction of pulse technology, logic circuits, electrical components, etc., can solve the problem of large hardware consumption, and achieve a simple structure, expanded width range, and strong anti-single event transient pulse ability Effect

Active Publication Date: 2016-03-02
SOI MICRO CO LTD
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method also needs to implement two stages of phase delay, as well as three latches and adjudication circuits, which consumes a lot of hardware

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Anti-single event transient pulse cmos circuit
  • Anti-single event transient pulse cmos circuit
  • Anti-single event transient pulse cmos circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0031] figure 1 It shows a schematic structural diagram of an anti-single event transient pulse circuit provided by an embodiment of the present invention, and the circuit includes:

[0032] The first buffer 101 is used to eliminate the "high low high" type pulse, its input terminal receives the input signal in, and its output terminal outputs the first buffer signal out1;

[0033] The second buffer 102 is used to eliminate the "low high low" type pulse, its input terminal receives the input signal in, and its output terminal outputs the second buffer signal out2;

[0034] The gate PMOS transistor 103 and the gate NMOS transistor 104, wherein the source electrode of the gate PMOS transistor 103 and the substrate are conn...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An single event transient (SET)-resistant CMOS circuit. The circuit consists of a first buffer (101), a second buffer (102), a gating PMOS transistor (103), a gating NMOS transistor (104) and a phase inverter (105); the first buffer is used for eliminating 'high-low-high' pulse, the input end of the first buffer is connected with the input end of an SET-resistant circuit, and the output end of the first buffer is connected with a grid of the gating PMOS transistor (103); the second buffer is used for eliminating 'low-high-low' pulse, the input end of the second buffer is connected with the input end of the SET-resistant circuit, and the output end of the second buffer is connected with a grid of the gating NMOS transistor (104). A drain of the gating PMOS transistor (103) is connected with a drain of the gating NMOS transistor (104) and serves as the input end of the phase inverter (105); and the output end of the phase inverter serves as the output end of the SET-resistant circuit.

Description

technical field [0001] The invention relates to the technical field of anti-radiation hardened circuits, in particular, the invention relates to an anti-single-event transient pulse CMOS circuit. Background technique [0002] Aerospace technology is an important symbol to measure a country's modernization level and comprehensive national strength. Integrated circuits are the core of spacecraft, and their performance and functions have become one of the main indicators for measuring the performance of various spacecraft. In order to meet the current and future challenges of aerospace technology development, countries are actively developing integrated circuits with high performance and high radiation resistance. In recent years, my country's aerospace industry has developed rapidly, and major aerospace applications such as manned spaceflight projects, lunar exploration projects, "Beidou" navigation and positioning systems, and "Tiangong" have put forward urgent needs for anti...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0948
CPCH03K19/0948H03K19/00338
Inventor 宿晓慧毕津顺罗家俊韩郑生郝乐
Owner SOI MICRO CO LTD