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Carrier warpage control for three dimensional integrated circuit (3DIC) stacking

A carrier, package stacking technology, used in circuits, electrical solid state devices, semiconductor/solid state device manufacturing, etc., can solve problems such as insufficient prevention of package warpage

Active Publication Date: 2014-03-12
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Unfortunately, conventional processes used to fabricate PoP devices may not be sufficient to prevent package warpage

Method used

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  • Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
  • Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
  • Carrier warpage control for three dimensional integrated circuit (3DIC) stacking

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Embodiment Construction

[0033] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0034] The invention is described in terms of existing embodiments in a specific context, namely, a package-on-package (PoP) semiconductor device. However, the concepts in the present invention can also be applied to other semiconductor structures or circuits.

[0035] Referring now to FIGS. 1A-1I , which collectively illustrate forming a PoP device 10 ( Figure 2-4 ) embodiment method. As shown in FIG. 1A , an adhesive 12 or other suitable bonding material is deposited or formed on a carrier 14 . In one embodiment, carrier 14 is formed from glass, silicon, a material...

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PUM

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Abstract

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application Serial No. 61 / 693,083, entitled "Carrier Warpage Control for 3DICStacking," filed August 24, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates generally to the field of semiconductors, and more particularly to carrier warpage control for three-dimensional integrated circuit (3DIC) stacks. Background technique [0004] With the demand for the development of electronic products with smaller volumes, manufacturers in the electronic industry are constantly looking for ways to reduce the size of integrated circuits used in electronic products. In view of this aspect, three-dimensional integrated circuit packaging technology has been developed and used. [0005] A package-on-package (PoP) technique has been developed. As the name suggests, PoP is a semiconductor packaging inven...

Claims

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Application Information

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IPC IPC(8): H01L21/58H01L21/60
CPCH01L24/83H01L2224/16145H01L24/96H01L23/3128H01L2924/15788H01L2224/97H01L2924/3511H01L2224/81005H01L24/13H01L2924/15311H01L2225/06541H01L2924/141H01L21/563H01L21/568H01L2924/1434H01L2224/32225H01L24/97H01L2924/15787H01L2224/92125H01L2924/18161H01L2924/157H01L24/81H01L2224/73204H01L25/0657H01L24/32H01L21/56H01L2225/06517H01L2924/0002H01L2225/06513H01L2224/32145H01L2224/83005H01L2224/131H01L24/16H01L24/92H01L2924/1431H01L2224/16225H01L2225/06562H01L2225/06565H01L21/561H01L24/73H01L2924/00012H01L2224/81H01L2924/014H01L2924/00H01L2224/17181H01L2924/351H01L23/12H01L23/14H01L23/48
Inventor 林俊成林士庭余振华
Owner TAIWAN SEMICON MFG CO LTD