Laminated chip wafer-level copper bump packaging structure

Abstract

The invention relates to a laminated chip wafer-level copper bump packaging structure which comprises a laminated chip composed of a first silicon bearing layer and a second silicon bearing layer, wherein the second silicon bearing layer is laid on the bottom of the first silicon bearing layer to form a bulge region; an electric insulating layer respectively grows on the bottom of the first silicon bearing layer and the bulge region, and a first opening and a second opening are left; a first electric connection point is arranged in the first opening; a second electric connection point is arranged in the second opening; a photoresistance layer grows on each electric insulating layer; a metal layer grows on the photoresistance layer; the metal layers are covered on the first electric connection point and the second electric connection point; the first electric connection point is subjected to repeated electroplating to form a first copper bump; the second electric connection point is subjected to repeated electroplating to form a second copper bump; the tops of the first copper bump and second copper bump are on the same horizontal surface; and metal balls with the same height grow on the tops of the first copper bump and second copper bump. The structure can ensure better connection in a flip-chip process.

Description

technical field [0001] The invention relates to wafer-level packaging in the technical field of semiconductor packaging, in particular to a wafer-level copper bump packaging structure for stacked chips. Background technique [0002] The current packaging technology is still traditional packaging as the mainstream, although after entering the 21st century, wafer-level advanced packaging has been widely used in image sensors, flash memory, logic devices, power chips and other industries, and the market share of advanced packaging has also been maintained year by year However, there are still many deficiencies in advanced packaging technology, and there are still many technical problems that need to be solved. Before these problems are solved, some chips must be packaged with traditional technology. [0003] The microelectronics industry is developing at a speed consistent with Moore's Law, which determines the integration of more field effect transistors, various resistors, ca...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a wafer-level copper bump packaging structure for stacked chips, which solves the problems of size, performance and cost caused by traditional packaging.

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