Method for Stable Reverse Link Data Rate of Radio Frequency Identification Tag Chip
A radio frequency identification tag and reverse link technology, applied in the field of stable reverse link data rate of radio frequency identification tag chips, to achieve the effect of low system power consumption
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[0028] In this embodiment, there are 4 clock oscillators on the ISO protocol tag chip. During the power-on stage of the chip, the 4 oscillators start to oscillate and output 4 different oscillation frequencies, which are f1=0.9MHz, f2=0.98MHz, f3=1.04MHz, f4=1.12MHz. At the initial stage of a communication, the reader sends a Query command to the tag chip, which contains link parameters DR=8, TRcal=25us. Expected value of reverse link data rate according to ISO protocol At this frequency point, the protocol allows the upper and lower limits of the error of the actual returned data rate to be ±10%.
[0029] After the tag chip confirms the two parameters of DR and TRcal, the division operation is performed first. In the hardware implementation of this embodiment, the division operation is completed by sampling, that is, four clocks f1 to f4 are used to sample the time length of TRcal respectively, and four sampling times are obtained: Q1=22, Q2=24, Q3= 26, Q4=28. Divide the n...
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