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Packaging structure

A technology of packaging structure and metal bumps, applied in the direction of electrical components, electric solid-state devices, circuits, etc., can solve the problems of improving, unfavorable packaging structure integration, large volume, etc., and achieves reduced area, increased distance, and small volume. Effect

Active Publication Date: 2014-04-23
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The existing packaging structure occupies a large volume, which is not conducive to the improvement of the integration of the packaging structure

Method used

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Embodiment Construction

[0032] The integration level of the existing packaging structure is low, please refer to figure 1 , the pins 16 in the existing packaging structure are arranged around the semiconductor chip 14, and the pads 15 on the semiconductor chip 14 need to be electrically connected to the surrounding pins 16 through metal wires 17, so that the entire packaging structure occupies The larger volume is not conducive to the improvement of the integration degree of the packaging structure.

[0033] The invention provides a packaging structure, the semiconductor chip is flip-chip on the pin, the second metal bump on the semiconductor chip and the first metal bump on the pin are welded together through a solder layer, and the volume occupied by the packaging structure is reduced. Small, improving the integration of the package structure.

[0034] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present inven...

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Abstract

A packaging structure comprises: a plurality of separated pins, wherein an opening is formed between adjacent pins; first metal protrusion blocks arranged on the surfaces of the pins; solder layers covering the tops and side walls of the first metal protrusion blocks; and a semiconductor chip, wherein the surface of the semiconductor chip is provided with bonding pads. Each bonding pad is provided with a second metal protrusion block. The semiconductor chip is inversely arranged above the pins. The second metal protrusion blocks on the semiconductor chip are welded with the first metal protrusion blocks on the pins through the solder layers. The integration level of the packaging structure is high.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging structure. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has been rapidly developed. Compared with expensive packaging forms such as BGA (Ball Grid Array), new packaging technologies that have developed rapidly in recent years, such as Quad Flat No-lead Package (QFN) due to its good thermal performance and electrical The advantages of performance, small size, low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology. [0003] figure 1 It is a structural schematic diagram of an existing QFN packaging structure...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488
CPCH01L2224/16245H01L2224/48091H01L2224/48247H01L2924/00014
Inventor 石明达石磊陶玉娟
Owner NANTONG FUJITSU MICROELECTRONICS