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Information processing apparatus and scheduling method

A technology of an information processing device and a scheduling method, applied in the field of information processing devices, can solve problems such as reduced processing efficiency, and achieve the effect of reducing power consumption

Inactive Publication Date: 2014-04-30
FUJITSU CLIENT COMPUTING LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when the computer system 100 grants access permission to the DMA request in fragments (for example, every few bytes), the processing efficiency of the entire system is reduced due to the repeated issuance and permission of the DMA request.

Method used

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  • Information processing apparatus and scheduling method
  • Information processing apparatus and scheduling method
  • Information processing apparatus and scheduling method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0064] Embodiments are described below with reference to the drawings.

[0065] [1] One embodiment

[0066] [1-1] Configuration example of information processing device

[0067] figure 1 is a diagram showing a configuration example of an information processing device 1 as an embodiment, figure 2 It is a diagram showing a configuration example of the bus arbiter 4 in the information processing device 1 .

[0068] The information processing device 1 is a computer system (multi-master system) such as a server or a PC, which has: at least one of a CPU core 21 and a CM 22 ( figure 1 In the illustrated example, there is one) CPU (processing unit) 2 ; and PCI devices 3 - 1 to 3 - 3 capable of executing DMA. In addition, the information processing device 1 has a bus arbiter 4 , timing adjusters (Timing Adjuster; hereinafter referred to as TA) 5 - 1 to 5 - 3 , a system bus 6 , a bus bridge 7 , a bus with a host bus 81 and a bus arbiter 82 . management unit 8 , storage controlle...

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Abstract

An information processing apparatus is provided with: at least one accessing unit (3) that issues a memory access request to a memory (10); an arbitration unit (4) that arbitrates memory access requests issued by the accessing unit (3); a management unit (8) that allows memory access to the memory (10) by an accessing unit (3) that is the issuing source of the memory access request conforming to the arbitration results of the arbitration unit (4); a processing unit (2) that executes the access to the memory (10) via at least one cache memory (22); and a timing adjustment unit (5) that suspends processing related to the memory access request issued by the accessing unit (3) for a prescribed suspension period, and cancels the suspension of the processing related to the memory access request when the power supply of the aforementioned at least one cache memory (22) of the processing unit (2) turns off before the suspension period elapses.

Description

technical field [0001] The present invention relates to an information processing apparatus having a device that issues a memory access request, and a method for scheduling processing related to the memory access request. Background technique [0002] In so-called computer systems such as servers and personal computers (PCs; Personal Computers), there is a method of using a system bus called DMA (Direct Memory Access). DMA refers to allowing a device (bus master) other than the CPU to use the system bus normally performed by a CPU (Central Processing Unit: Central Processing Unit). In addition, in a multiprocessor system with multiple CPUs (or CPU cores), it is designed that the multiple CPUs coordinate with each other to use the system bus. [0003] Also, a system in which there are a plurality of devices (including CPUs) that allow the use of the system bus is called a multi-master system, and a bus used in the multi-master system is called a multi-master bus. [0004] I...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0802G06F13/1605G06F12/08G06F13/1689G06F13/00Y02D10/00
Inventor 小池信之宫本十四广
Owner FUJITSU CLIENT COMPUTING LTD