Semiconductor device manufacturing method

Abstract

This invention discloses a manufacture method for semiconductor devices, comprising a plurality of dummy gate stacks formed on a substrate, a plurality of first side walls on two sides of each dummy gate stack and a plurality of first layer interlaminar dielectric layers among the plurality of the first side walls. The steps of the manufacture method comprises steps of removing dummy gate stacks and first layer interlaminar dielectric layers and leaving the plurality of first side walls on the substrate, forming a plurality of second layers which are on two sides of each side wall on the substrate, forming second interlaminar dielectric layers among the plurality of the second side walls, removing the first side walls and the second side walls and forming a plurality of source-drain channels, forming a third layer interlaminar dielectric layer in each source-drain channel, removing the second layer interlaminar dielectric layers and forming gate channels, and forming gate stacks in the gate channels. According to the manufacture method for the semiconductor devices disclosed by the invention, the gate channels are formed through multiple times and step-by-step and through the adoption of the combination of the plurality of side walls and the interlaminar dielectric layers, which reduces the line width of the final gate stack and improves the performance and the reliability of the semiconductor device is improved.

Description

technical field [0001] The invention relates to a semiconductor device manufacturing method, in particular to a semiconductor device manufacturing method capable of effectively controlling the fineness of lines. Background technique [0002] After MOSFET devices are scaled down to 45nm, the device requires a stack structure of high dielectric constant (high k) as the gate insulating layer and metal as the gate conductive layer to suppress high gate leakage due to polysilicon gate depletion issues and the gate capacitance is reduced. In order to control the profile of the gate stack more effectively, the gate-last process is widely used in the industry, that is, the dummy gates made of polysilicon and other materials are usually deposited on the substrate first, and the dummy gates are removed after depositing the interlayer dielectric layer (ILD). gate, followed by filling the remaining gate trenches with a stack of high-k / metal gate (HK / MG) film layers. [0003] However, ...

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Problems solved by technology

[0003] However, in the above-mentioned gate last process, due to the limitation of the development of photolithography / etching process, it is difficult to accurately control the line width of small-sized devices by using traditional single etching-filling, especially when the current feature size has been reduced to below 22nm, Even 10nm stage

In the manufacturing process of these small-sized devices, it is often difficult to achieve a complete vertical shape of the dummy gate layer, and it is also difficult to uniformize the width / spacing of the gate line itself and between multiple lines, resulting in a large error in line width , reducing the reliability of the device

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